METROLOGY DATA CORRECTION USING IMAGE QUALITY METRIC

    公开(公告)号:WO2020035516A1

    公开(公告)日:2020-02-20

    申请号:PCT/EP2019/071774

    申请日:2019-08-14

    Abstract: Described herein is a method for correcting metrology data of a patterning process. The method includes obtaining (P92) (i) metrology data (901) of a substrate subjected to the patterning process and (ii) a quality metric (902, e.g., a focus index) that quantifies a quality of the metrology data of the substrate; establishing (P94) a correlation between the quality metric and the metrology data; and determining (P96) a correction to the metrology data based on the correlation between the quality metric and the metrology data.

    MASK DEFECT DETECTION
    2.
    发明申请

    公开(公告)号:WO2023016723A1

    公开(公告)日:2023-02-16

    申请号:PCT/EP2022/069169

    申请日:2022-07-08

    Abstract: An improved methods and systems for detecting defect(s) on a mask are disclosed. An improved method comprises inspecting an exposed wafer after the wafer was exposed, by a lithography system using a mask, with a selected process condition that is determined based on a mask defect printability under the selected process condition; and identifying, based on the inspection, a wafer defect that is caused by a defect on the mask to enable identification of the defect on the mask.

    PROCESS WINDOW BASED ON FAILURE RATE
    3.
    发明申请

    公开(公告)号:WO2022002599A1

    公开(公告)日:2022-01-06

    申请号:PCT/EP2021/066324

    申请日:2021-06-17

    Abstract: Described herein is a method for determining a process window of a patterning process based on a failure rate. The method includes (a) obtaining a plurality of features printed on a substrate, (b) grouping, based on a metric, the features into a plurality of groups, and (c) generating, based on measurement data associated with a group of features, a base failure rate model for the group of features, wherein the base failure rate model identifies the process window related to the failure rate of the group of features. The method further includes generating, using the base failure rate model, a feature-specific failure rate model for a specific feature, wherein the feature-specific failure rate model identifies a feature-specific process window such that an estimated failure rate of the specific feature is below a specified threshold.

    SEMICONDUCTOR DEVICE GEOMETRY METHOD AND SYSTEM

    公开(公告)号:WO2021037484A1

    公开(公告)日:2021-03-04

    申请号:PCT/EP2020/071741

    申请日:2020-07-31

    Abstract: Systems and methods for predicting substrate geometry associated with a patterning process are described. Input information including geometry information and/or process information for a pattern are received; and, using a machine learning prediction model, multi-dimensional output substrate geometry is predicted. The multi-dimensional output information comprises pattern probability images. A stochastic edge placement error band and/or a stochastic failure rate may be predicted based on the pattern probability images. The input information comprises simulated aerial images, simulated resist images, target substrate dimensions, and/or data from a scanner associated with semiconductor device manufacturing. Different aerial images may correspond to different heights in resist layers associated with the patterning process, for example.

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