公开(公告)号：US09560753B2

公开(公告)日：2017-01-31

申请号：US15016212

申请日：2016-02-04

Applicant: TM TECHNOLOGY, INC

Inventor： Ben Wu ,  Wen-Doe Su

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/0298 ,  H01L33/62 ,  H01L33/64 ,  H01L2224/16225 ,  H01L2933/0075 ,  H05K1/09 ,  H05K1/111 ,  H05K3/0017 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2201/10106 ,  H05K2201/10242 ,  H05K2203/0562

Abstract: A light emitting diode load board includes a substrate, a first dielectric layer, a second dielectric layer and a first conductive pad and a second conductive pad. The second dielectric layer includes a first structure part, a second structure part and a third structure part. The first dielectric layer is disposed on the substrate. The first structure part is disposed on the first dielectric layer and has a first sidewall. The second structure part is disposed on the first structure part and has a second sidewall. The third structure part is disposed on the second structure part and has N sidewalls. The second sidewall is more prominent than the first sidewall. The first sidewall, the second sidewall and the N sidewalls define the first etched part, and the part of the first dielectric layer is exposed from the first etched part. The first conductive pad is disposed in the first etched part. The second conductive is disposed on the second dielectric layer, covers part of the second dielectric and exposes the open of the first etched part.

Abstract translation: 发光二极管负载板包括衬底，第一电介质层，第二电介质层和第一导电焊盘和第二导电焊盘。 第二电介质层包括第一结构部分，第二结构部分和第三结构部分。 第一介电层设置在基板上。 第一结构部分设置在第一电介质层上并具有第一侧壁。 第二结构部分设置在第一结构部分上并且具有第二侧壁。 第三结构部分设置在第二结构部分上并具有N个侧壁。 第二侧壁比第一侧壁更突出。 第一侧壁，第二侧壁和N侧壁限定第一蚀刻部分，并且第一电介质层的一部分从第一蚀刻部分露出。 第一导电焊盘设置在第一蚀刻部分中。 第二导体设置在第二电介质层上，覆盖第二电介质的一部分并暴露第一蚀刻部分的开口。

公开(公告)号：US09502322B2

公开(公告)日：2016-11-22

申请号：US14522760

申请日：2014-10-24

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H05K1/11 ,  H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H05K3/40 ,  H01L23/14 ,  H01L21/48 ,  H05K1/02 ,  H05K3/46 ,  H05K3/28

CPC classification number: H01L23/14 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/111 ,  H05K3/28 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/096 ,  H05K2201/10242 ,  H05K2201/10378 ,  H05K2203/07 ,  H05K2203/14

Abstract: One of the embodiments for a package substrate discloses a molding compound having plurality of metal pillar with middle portion embedded therein; a top end of the metal pillar protrudes above the molding compound; a bottom end of the metal pillar protrudes below the molding compound; a bottom RDL is configured on bottom of the molding compound; the RDL has a plurality of top metal pad and a plurality of bottom metal pad; a density of the plurality of bottom metal pad is higher than the density of the plurality of top metal pad; each metal pillar metal pad is electrically coupled to a corresponding first top metal pad.

Abstract translation: 封装基板的一个实施例公开了一种具有多个嵌入其中部的金属支柱的模塑料; 金属柱的顶端突出于模塑料上方; 金属柱的底端突出于模塑料下方; 底部RDL配置在模塑料的底部; RDL具有多个顶部金属焊盘和多个底部金属焊盘; 多个底部金属垫的密度高于多个顶部金属垫的密度; 每个金属支柱金属垫电耦合到相应的第一顶部金属垫。

公开(公告)号：US09491859B2

公开(公告)日：2016-11-08

申请号：US13901398

申请日：2013-05-23

Applicant: Massachusetts Institute of Technology

Inventor： Dmitry Tolpin ,  James H. Kelly ,  Roger M. Maurais

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34

CPC classification number: H05K3/301 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/351 ,  H01L2924/381 ,  H05K1/111 ,  H05K1/18 ,  H05K1/181 ,  H05K3/30 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2201/09427 ,  H05K2201/10242 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49133 ,  H01L2924/00

Abstract: Reliability is improved for the mechanical electrical connection formed between a grid array device, such as a pin grid array device (PGA) or a column grid array device (CGA), and a substrate such as a printed circuit board (PCB). Between adjacent PCB pads, a spacing pattern increases toward the periphery of the CGA, creating a misalignment between pads and columns. As part of the assembly method, columns align with the pads, resulting in column tilt that increases from the center to the periphery of the CGA. An advantage of this tilt is that it reduces the amount of contractions and expansions of columns during thermal cycling, thereby increasing the projected life of CGA. Another advantage of the method is that it reduces shear stress, further increasing the projected life of the CGA.

Abstract translation: 对于诸如针阵列阵列器件（PGA）或列格栅阵列器件（CGA）的栅格阵列器件和诸如印刷电路板（PCB）的衬底之间形成的机械电连接，可靠性得到改善。 在相邻的PCB焊盘之间，间隔图案朝向CGA的周边增加，导致焊盘和柱之间的未对准。 作为组装方法的一部分，列与焊盘对准，导致从CGA的中心到外围增加的列倾斜。 这种倾斜的一个优点是在热循环期间减少了柱的收缩量和膨胀量，从而增加了CGA的预计使用寿命。 该方法的另一个优点是降低了剪切应力，进一步提高了CGA的寿命。

公开(公告)号：US20160071789A1

公开(公告)日：2016-03-10

申请号：US14479377

申请日：2014-09-08

Applicant: Pei Fan Tong ,  Boon Yew Low ,  Lan Chu Tan

Inventor： Pei Fan Tong ,  Boon Yew Low ,  Lan Chu Tan

IPC: H01L23/498 ,  H05K3/34 ,  H01L21/52 ,  H05K1/18 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K3/0014 ,  H05K3/0044 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/4046 ,  H05K3/4688 ,  H05K2201/09118 ,  H05K2201/10242 ,  H05K2201/10378 ,  H05K2203/0235

Abstract: A method for forming a pass-through layer of an interposer of a packaged semiconductor device in which conducting structures are extended between first and second ends of a casing. The conducting structures are subsequently encapsulated in a molding compound to form a molded bar, and the molded bar is sliced to obtain the pass-through layer. The pass-through layer has conducting vias, each corresponding to a sliced section of one of the conducting structures. The cost of pass-through layers formed in this manner may be less than that of comparable silicon or glass pass-through layers.

Abstract translation: 一种用于形成封装半导体器件的中介层的贯穿层的方法，其中导电结构在壳体的第一和第二端之间延伸。 然后将导电结构封装在模塑料中以形成模制棒，并将模制棒切片以获得穿透层。 穿通层具有导电孔，每个对应于一个导电结构的切片部分。 以这种方式形成的直通层的成本可能低于可比较的硅或玻璃直通层的成本。

公开(公告)号：US20150235991A1

公开(公告)日：2015-08-20

申请号：US14254494

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim

IPC: H01L25/065 ,  H05K1/11 ,  H01L23/00 ,  H05K1/09 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L25/0655 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/17 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09845 ,  H05K2201/10242 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00

Abstract: A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate.

Abstract translation: 提供了底部封装基板，其包括多个金属柱，其通过裸片侧再分配层电耦合到多个管芯互连。 金属柱和管芯互连电镀在底部封装衬底上的晶种层上。

公开(公告)号：US20150163909A1

公开(公告)日：2015-06-11

申请号：US14000566

申请日：2012-06-19

Applicant: SHENNAN CIRCUITS CO LTD.

Inventor： Chuanzhi Li ,  Hua Miao ,  Zhanhao Xie ,  Jun Peng

IPC: H05K1/11 ,  H05K3/00 ,  H05K1/02

CPC classification number: H05K1/115 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0243 ,  H05K1/0298 ,  H05K3/0094 ,  H05K3/4635 ,  H05K2201/0792 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09618 ,  H05K2201/09845 ,  H05K2201/10242 ,  H05K2201/10416 ,  Y10T29/49165

Abstract: A printed circuit board (PCB) a method for processing PCB and an electronic apparatus are provided. The method for processing PCB may include: forming a hole in the PCB, wherein the PCB includes a metal matrix and at least two substrate layers, at least one of the at least two substrate layers has an geoelectric layer thereon; the metal matrix is fixed in a slot provided its the substrate, the formed hole contacts with both the geoelectric layer and the metal matrix; and providing conductive substances in the hole, with the conductive substances in the hole being in contact with the inner geoelectric layer and the metal matrix, so that the inner geoelectric layer and the metal matrix are in conduction with each other. The solutions of the embodiments of the application are beneficial to improve reliability of connection between the geoelectric layer and the metal matrix of the PCB, and improve transmission performance of a high frequency signal.

Abstract translation: 提供印刷电路板（PCB）用于处理PCB和电子设备的方法。 用于处理PCB的方法可以包括：在PCB中形成孔，其中PCB包括金属基体和至少两个基底层，至少两个基底层中的至少一个在其上具有地电层; 金属基体固定在设置其基板的槽中，形成的孔与地电电极和金属基体接触; 并且在孔中提供导电物质，孔中的导电物质与内部地电电极和金属基体接触，使得内部地电电介质层和金属基体彼此导通。 本申请的实施例的解决方案有利于提高PCB上的地电层和金属矩阵之间的连接的可靠性，并提高高频信号的传输性能。

公开(公告)号：US20150136468A1

公开(公告)日：2015-05-21

申请号：US14538684

申请日：2014-11-11

Applicant: FINISAR CORPORATION

Inventor： Henry Meyer Daghighian ,  Steven C. Bird ,  YongShan Zhang

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K3/4046 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/0094 ,  H05K2201/0959 ,  H05K2201/09636 ,  H05K2201/10242 ,  Y10T29/49165

Abstract: Some embodiments relate to micro vias in printed circuit boards (PCBs). In an example, a PCB may include a PCB substrate and a micro via. The micro via may extend between opposing surfaces of the PCB substrate and may have a diameter less than or equal to about 100 microns. In another example, a method of forming micro vias in a PCB may include forming a through hole in a PCB substrate of the PCB. The method may also include positioning a pillar that is electrically conductive within the through hole. The method may also include backfilling the through hole around the pillar with an epoxy backfill.

Abstract translation: 一些实施例涉及印刷电路板（PCB）中的微通孔。 在一个示例中，PCB可以包括PCB基板和微通孔。 微通孔可以在PCB基板的相对表面之间延伸并且可以具有小于或等于约100微米的直径。 在另一示例中，在PCB中形成微通孔的方法可以包括在PCB的PCB衬底中形成通孔。 该方法还可以包括定位在通孔内导电的支柱。 该方法还可以包括用环氧填充物填充柱周围的通孔。

公开(公告)号：US20140264788A1

公开(公告)日：2014-09-18

申请号：US14090560

申请日：2013-11-26

Applicant: FUJITSU LIMITED

Inventor： Satoshi MASUDA

IPC: H01L23/66

CPC classification number: H05K7/026 ,  H01L23/045 ,  H01L23/047 ,  H01L23/3677 ,  H01L23/49833 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/162 ,  H01L2224/06181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/16195 ,  H01L2924/1627 ,  H01L2924/19107 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K3/4697 ,  H05K7/20509 ,  H05K9/0039 ,  H05K2201/0919 ,  H05K2201/09845 ,  H05K2201/10242 ,  H05K2201/10371 ,  H05K2201/1056 ,  H01L2224/45099

Abstract: A high-frequency module includes a lower base member having a recess part formed in an upper face thereof, and having a base metal part formed on a lower face thereof that is to be grounded, an upper substrate disposed inside the recess part of the lower base member, a semiconductor device mounted on an upper face of the upper substrate, a first ground line connected to the semiconductor device and formed on the upper substrate, and a ground metal part connected to the base metal part and disposed in the lower base member, wherein the ground metal part is connected to the first ground line on the upper substrate.

Abstract translation: 高频模块包括下基部件，其具有形成在其上表面中的凹部，并且具有形成在其下表面上的待接地的基底金属部分，设置在下部的凹部内的上基板 基底构件，安装在上基板的上表面上的半导体器件，连接到半导体器件并形成在上基板上的第一接地线，以及连接到基底金属部分并设置在下基底构件中的接地金属部件 ，其中所述接地金属部分连接到所述上基板上的所述第一接地线。

公开(公告)号：US20140247269A1

公开(公告)日：2014-09-04

申请号：US13784580

申请日：2013-03-04

Applicant: QUALCOMM MEMS Technologies, Inc.

Inventor： David Francis Berdy ,  Jonghae Kim ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Je-Hsiung Jeffrey Lan

IPC: H01F17/00 ,  H01F41/14 ,  G06T1/00

CPC classification number: H01F17/0006 ,  G06T1/00 ,  H01F1/24 ,  H01F1/37 ,  H01F17/0033 ,  H01F41/046 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49822 ,  H01L28/10 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/165 ,  H05K3/4046 ,  H05K2201/086 ,  H05K2201/09063 ,  H05K2201/097 ,  H05K2201/10242 ,  H01L2924/00

Abstract: This disclosure provides systems, methods and apparatus for three-dimensional (3-D) through-glass via inductors. In one aspect, the through-glass via inductor includes a glass substrate with a first cavity, a second cavity, and at least two through-glass vias. The through-glass vias include metal bars that are connected by a metal trace. The metal bars and the metal trace define the inductor, and each cavity is at least partially filled with magnetic material. The magnetic material can include a plurality of particles having an average diameter of less than about 20 nm. The first cavity can be inside the inductor and the second cavity can be outside inductor. In some implementations, the first and the second cavity can be vias that extend only partially through the glass substrate.

Abstract translation: 本公开提供用于三维（3-D）透玻璃通孔电感器的系统，方法和装置。 一方面，透玻璃通孔电感器包括具有第一空腔，第二空腔和至少两个透玻璃通孔的玻璃基板。 透玻璃通孔包括通过金属迹线连接的金属棒。 金属棒和金属迹线限定电感器，并且每个空腔至少部分地填充有磁性材料。 磁性材料可以包括平均直径小于约20nm的多个颗粒。 第一个腔可以在电感内部，第二个腔可以是外部电感。 在一些实施方案中，第一和第二腔可以是仅部分延伸穿过玻璃基底的通孔。

公开(公告)号：US20140211421A1

公开(公告)日：2014-07-31

申请号：US13752584

申请日：2013-01-29

Applicant: Matthew D. Mishrikey ,  James O'Keeffe ,  Bruce R. Conway ,  Peter J. Dutton

Inventor： Matthew D. Mishrikey ,  James O'Keeffe ,  Bruce R. Conway ,  Peter J. Dutton

IPC: H05K1/02

CPC classification number: H05K1/144 ,  H01L2224/16225 ,  H05K1/0209 ,  H05K2201/042 ,  H05K2201/066 ,  H05K2201/10242 ,  H05K2201/2036

Abstract: A circuit board assembly includes first and second circuit boards that each have a substrate and a conductive circuit layer positioned on the substrate. The first and second circuit boards are arranged such that the conductive circuit layers face each other across a gap. Thermal conductor pillars extend lengths across the gap between the conductive circuit layers of the first and second circuit boards. The thermal conductor pillars include opposite first and second ends that are engaged in thermal contact with the conductive circuit layers of the first and second circuit boards, respectively. The thermal conductor pillars provide thermal pathways for heat to travel between the first and second circuit boards.

Abstract translation: 电路板组件包括第一和第二电路板，每个电路板具有衬底和位于衬底上的导电电路层。 第一和第二电路板布置成使得导电电路层跨越间隙彼此面对。 热导体支柱跨越第一和第二电路板的导电电路层之间的间隙延伸长度。 热导体柱包括分别与第一和第二电路板的导电电路层热接触的相对的第一和第二端。 热导体柱提供用于热在第一和第二电路板之间行进的热路径。