公开(公告)号：US20210158155A1

公开(公告)日：2021-05-27

申请号：US16992354

申请日：2020-08-13

Applicant: NVIDIA Corp.

Inventor： Yanqing Zhang ,  Haoxing Ren ,  Brucek Khailany

IPC: G06N3/08 ,  G06N3/04 ,  G06N5/04 ,  G06K9/62 ,  G06F11/30 ,  G06F11/34

Abstract: A graph neural network for average power estimation of netlists is trained with register toggle rates over a power window from an RTL simulation and gate level netlists as input features. Combinational gate toggle rates are applied as labels. The trained graph neural network is then applied to infer combinational gate toggle rates over a different power window of interest and/or different netlist.

公开(公告)号：US20210124558A1

公开(公告)日：2021-04-29

申请号：US16803795

申请日：2020-02-27

Applicant: NVIDIA Corp.

Inventor： Ilyas Elkin ,  Ge Yang ,  Xi Zhang

IPC: G06F7/501 ,  G06F7/575 ,  G06F9/30

Abstract: An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

公开(公告)号：US10979176B1

公开(公告)日：2021-04-13

申请号：US16792154

申请日：2020-02-14

Applicant: NVIDIA Corp.

Inventor： Sunil Sudhakaran ,  Rohit Rathi

IPC: H04L1/00 ,  H04L1/08 ,  H04L25/03

Abstract: Techniques for limiting the growth of errors in decoded data words that arise from bit errors incurred during transmission. The growth of 3+ bit errors in the decoded data word is limited at the expense of a higher number of two bit errors, which are correctable using practical error correcting codes.

公开(公告)号：US20210083837A1

公开(公告)日：2021-03-18

申请号：US16927017

申请日：2020-07-13

Applicant: NVIDIA Corp.

Inventor： Xi Chen ,  Nikola Nedovic ,  Carl Thomas Gray ,  Stephen G Tell

IPC: H04L7/00

Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

公开(公告)号：US20210083836A1

公开(公告)日：2021-03-18

申请号：US16905635

申请日：2020-06-18

Applicant: NVIDIA Corp.

Inventor： Xi Chen ,  Nikola Nedovic ,  Carl Thomas Gray ,  Stephen G. Tell

IPC: H04L7/00 ,  H03K3/037 ,  H04B1/12 ,  H04B1/16

Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

公开(公告)号：US20210004235A1

公开(公告)日：2021-01-07

申请号：US17024683

申请日：2020-09-17

Applicant: NVIDIA Corp.

Inventor： Siva Kumar Sastry Hari ,  Michael Sullivan ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F11/14 ,  G06F11/07

Abstract: A thread execution method in a processor includes executing original instructions of a first thread in a first execution lane of the processor, and interleaving execution of duplicated instructions of the first thread with execution of original instructions of a second thread in a second execution lane of the processor.

公开(公告)号：US10820057B2

公开(公告)日：2020-10-27

申请号：US16376988

申请日：2019-04-05

Applicant: NVIDIA Corp.

Inventor： Hans Eberle ,  Larry Robert Dennison

IPC: H04N21/472 ,  H04N21/2387 ,  H04N21/6583 ,  H04L12/743 ,  H04N21/43 ,  H04L12/841 ,  H04L12/733 ,  H04N21/234 ,  H04L12/863

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

公开(公告)号：US20200336286A1

公开(公告)日：2020-10-22

申请号：US16802437

申请日：2020-02-26

Applicant: NVIDIA Corp.

Inventor： Pervez Mirza Aziz ,  Vishnu Balan ,  Viswanath Annampedu

IPC: H04L7/033 ,  H04L25/03 ,  H04L7/00

Abstract: A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.

公开(公告)号：US20200327417A1

公开(公告)日：2020-10-15

申请号：US15929242

申请日：2020-03-17

Applicant: NVIDIA Corp.

Inventor： Zhiyao Xie ,  Haoxing Ren ,  Brucek Khailany ,  Sheng Ye

IPC: G06N3/08 ,  G06N3/04 ,  G06F30/398

Abstract: IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.

公开(公告)号：US10754775B2

公开(公告)日：2020-08-25

申请号：US16222696

申请日：2018-12-17

Applicant: NVIDIA Corp.

Inventor： Jay Gupta ,  Gosagan Padmanabhan ,  Devesh Mittal ,  Kaushal Agarwal

IPC: G06F12/0808 ,  G06F12/1045

Abstract: A memory management unit responds to an invalidate by class command by identifying a marker for a class of cache entries that the invalidate by class command is meant to invalidate. The memory management unit stores the active marker as a retired marker and then sets the active marker to the next available marker. Thereafter, the memory management sends an acknowledgement signal (e.g., to the operating system) while invalidating the cache entries having the class and the retired marker in the background. By correlating markers with classes of cache entries, the memory management can more quickly respond to class invalidation requests.