公开(公告)号：US07821111B2

公开(公告)日：2010-10-26

申请号：US11867821

申请日：2007-10-05

Applicant: John Tellkamp

Inventor： John Tellkamp

IPC: H01L23/495 ,  H01L23/28

CPC classification number: H01L23/49548 ,  H01L21/4828 ,  H01L21/4842 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3426 ,  H05K2201/10689 ,  H05K2201/10848 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 μm deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 μm deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions.

Abstract translation: 封装的表面贴装半导体器件具有构造在五个相邻部分中的外部未封装引线段：第一部分围绕水平从封装突出; 第二部分向下形成凸起的弯曲部分; 第三部分大致直线向下; 第四部分向上形成凹弯; 第五部分是水平的。 每个段在宽度上具有第三部分中的第一凹槽，无论是在底表面上还是在顶表面上。 优选地，凹槽在垂直于第五引线部分的底表面上的约2个引线框厚度。 当冲压时，凹槽可以具有约5和50μm深的角轮廓; 当蚀刻时，凹槽可以具有约50至125μm深的近似半圆形轮廓。 第二槽可以位于第二段部分中; 第三凹槽可以位于从第三分段部分到第四分段部分的过渡区域中。

公开(公告)号：US6040623A

公开(公告)日：2000-03-21

申请号：US795056

申请日：1997-02-05

Applicant: Min Yu Chan ,  Jing Sua Goh

Inventor： Min Yu Chan ,  Jing Sua Goh

IPC: H01L23/495 ,  H05K1/02 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L23/49541 ,  H05K3/3426 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K2201/10689 ,  H05K2201/1084 ,  H05K2201/10848 ,  Y02P70/613 ,  Y10T29/49144

Abstract: A lead (10) for a semiconductor device (12) comprising a strip portion (14) comprising a first substantially horizontal portion (18) connected to the semiconductor device (12), a substantially vertical portion (20) connected to the first substantially horizontal portion (18), and a second substantially horizontal portion (22) connected to the substantially vertical portion (20) with at least one hole (16) disposed in the strip portion (14). A method of providing an electrical contact for connecting a semiconductor device (12) to a surface (24) comprising the steps of extending at least one lead (10) from the semiconductor device (12) and slotting the lead (10).

Abstract translation: 一种用于半导体器件（12）的引线（10），包括带状部分（14），所述带状部分包括连接到所述半导体器件（12）的第一基本上水平的部分（18），大致垂直部分（20），连接到所述第一基本水平 以及连接到大致垂直部分（20）的第二基本上水平的部分（22），其中至少一个孔（16）设置在带状部分（14）中。 一种提供用于将半导体器件（12）连接到表面（24）的电触点的方法，包括以下步骤：从半导体器件（12）延伸至少一个引线（10）并对引线（10）进行开槽。

公开(公告)号：US6011693A

公开(公告)日：2000-01-04

申请号：US977247

申请日：1997-11-24

Applicant: John G. Gore

Inventor： John G. Gore

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/28 ,  H05K3/30 ,  H05K3/34 ,  H05K3/36 ,  H01L41/053

CPC classification number: H05K1/141 ,  H05K1/0243 ,  H05K3/303 ,  H05K3/3426 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/3447 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/3025 ,  H05K1/0271 ,  H05K2201/049 ,  H05K2201/09063 ,  H05K2201/09081 ,  H05K2201/09181 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10083 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10727 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10848 ,  H05K2201/10871 ,  H05K2201/10946 ,  H05K2201/10969 ,  H05K2201/10984 ,  H05K2203/041 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/368 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49144

Abstract: A surface mounting stress relief system for mounting a surface mount package such as a leadless ceramic chip carrier on a printed circuit board includes a printed circuit board having a top layer attached to a bottom layer. The top layer includes cavities for exposing top surface portion of the bottom layer which carry a plurality of solder pads. The surface mount package is positioned on the printed circuit board for placing the package bottom surface on a top surface of the printed circuit board between the cavities while positioning package contact pads in spaced relation above corresponding preselected solder pads. A solder column extends between each of the plurality of corresponding solder pads and the selected contact pads for providing an electrical connection. The solder column is formed by applying a solder paste to the solder pads on the printed circuit board, screening a low temperature solder paste onto each of the contact pads of the surface mount package, placing a solder ball onto each pad, and attaching the solder ball to each of the contact pads of the package by passing the package through a reflow oven for reflowing the low temperature solder paste without reflowing the high temperature solder ball.

Abstract translation: 用于将诸如无引线陶瓷芯片载体的表面贴装封装安装在印刷电路板上的表面安装应力消除系统包括具有连接到底层的顶层的印刷电路板。 顶层包括用于暴露底层的顶表面部分的空腔，其承载多个焊盘。 表面安装封装位于印刷电路板上，用于将封装底表面放置在印刷电路板的上表面之间，同时将封装接触焊盘定位在相应的预选焊盘上方。 焊料柱在多个对应的焊盘和所选择的接触焊盘中的每一个之间延伸以提供电连接。 焊料柱通过将焊膏涂布到印刷电路板上的焊盘上而形成，将低温焊膏筛选到表面贴装封装的每个接触焊盘上，将焊球放置在每个焊盘上，并将焊料 通过使包装通过回流炉以回流低温焊膏而不回流高温焊球，从而将其包裹到每个接触焊盘。

公开(公告)号：US5834366A

公开(公告)日：1998-11-10

申请号：US914469

申请日：1997-08-19

Applicant: Salman Akram

Inventor： Salman Akram

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/32 ,  H01L23/48 ,  H01L23/498 ,  H05K1/02 ,  H05K3/32 ,  H05K3/40 ,  H01L21/44

CPC classification number: H01L24/12 ,  H01L21/4853 ,  H01L23/32 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/72 ,  H05K3/4007 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/73251 ,  H01L2224/81901 ,  H01L24/02 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H05K1/0271 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10848 ,  H05K3/326

Abstract: A method for forming an interconnect for making a temporary or permanent electrical connection to a semiconductor dice is provided. The method includes forming a substrate with an insulating layer and a pattern of conductors thereon. The conductors are formed as a bi-metal stack including a barrier layer formed of an inert metal and a conductive layer formed of a highly conductive metal. Microbumps are formed on the conductors by deposition through a mask using an electroplating, electroless plating, screen printing or evaporation process. The interconnect can be used to provide a temporary electrical connection for testing bare semiconductor dice. Alternately the interconnect can be used for flip chip mounting dice for fabricating multi chip modules and other electronic devices.

Abstract translation: 提供了一种用于形成用于制造与半导体裸片的暂时或永久电连接的互连的方法。 该方法包括在其上形成具有绝缘层和导体图案的衬底。 导体形成为包括由惰性金属形成的阻挡层和由高导电性金属形成的导电层的双金属叠层。 通过使用电镀，无电镀，丝网印刷或蒸发工艺通过掩模沉积，在导体上形成微胶囊。 互连可用于提供用于测试裸半导体裸片的临时电连接。 或者，互连可以用于倒装芯片安装芯片，用于制造多芯片模块和其他电子设备。

公开(公告)号：US5808360A

公开(公告)日：1998-09-15

申请号：US647749

申请日：1996-05-15

Applicant: Salman Akram

Inventor： Salman Akram

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/32 ,  H01L23/48 ,  H01L23/498 ,  H05K1/02 ,  H05K3/32 ,  H05K3/40 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/12 ,  H01L21/4853 ,  H01L23/32 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/72 ,  H05K3/4007 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/73251 ,  H01L2224/81901 ,  H01L24/02 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H05K1/0271 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10848 ,  H05K3/326

Abstract: A method for forming an interconnect for making a temporary or permanent electrical connection to a semiconductor dice is provided. The method includes forming a substrate with an insulating layer and a pattern of conductors thereon. The conductors are formed as a bi-metal stack including a barrier layer formed of an inert metal and a conductive layer formed of a highly conductive metal. Microbumps are formed on the conductors by deposition through a mask using an electroplating, electroless plating, screen printing or evaporation process. The interconnect can be used to provide a temporary electrical connection for testing bare semiconductor dice. Alternately the interconnect can be used for flip chip mounting dice for fabricating multi chip modules and other electronic devices.

Abstract translation: 提供了一种用于形成用于制造与半导体裸片的暂时或永久电连接的互连的方法。 该方法包括在其上形成具有绝缘层和导体图案的衬底。 导体形成为包括由惰性金属形成的阻挡层和由高导电性金属形成的导电层的双金属叠层。 通过使用电镀，无电镀，丝网印刷或蒸发工艺通过掩模沉积在导体上形成微胶囊。 互连可用于提供用于测试裸半导体裸片的临时电连接。 或者，互连可以用于倒装芯片安装芯片，用于制造多芯片模块和其他电子设备。

公开(公告)号：US5367124A

公开(公告)日：1994-11-22

申请号：US84643

申请日：1993-06-28

Applicant: Herman S. Hoffman ,  Richard W. Noth

Inventor： Herman S. Hoffman ,  Richard W. Noth

IPC: H01L23/50 ,  B23K1/00 ,  H01L23/495 ,  H01R4/02 ,  H05K1/02 ,  H05K3/34 ,  H01H9/02

CPC classification number: B23K1/0016 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/49582 ,  H05K3/3426 ,  B23K2201/36 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/14 ,  H01R12/57 ,  H01R4/028 ,  H05K1/0271 ,  H05K2201/10424 ,  H05K2201/10689 ,  H05K2201/10848 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613

Abstract: A compliant lead for electromechanically surface mounting an integrated circuit chip package to a substrate. The compliant lead extends from the package and includes at least two regions of different lead thickness. In a first region, a standard lead thickness is employed to ensure the applicability of existing package fabrication techniques. A second region, having a reduced thickness, then extends from the first region and is predefined to encompass an area of the lead expected to undergo greatest stress during thermal cycling. Compliancy is further guaranteed by providing a solder dam within the region of reduced thickness to limit wicking of solder when the package is solder mounted to the substrate. Lead frame fabrication is also discussed.

Abstract translation: 用于将集成电路芯片封装机械地表面安装到衬底的柔性引线。 柔性引线从封装延伸并且包括不同引线厚度的至少两个区域。 在第一区域中，使用标准铅厚度来确保现有封装制造技术的适用性。 具有减小的厚度的第二区域然后从第一区域延伸并且被预定义以包含期望在热循环期间经受最大应力的引线的区域。 通过在厚度较小的区域内提供焊锡坝，以便在封装焊接到基板上时限制焊料的芯吸，进一步保证了兼容性。 引线框架制造也被讨论。

公开(公告)号：US4257668A

公开(公告)日：1981-03-24

申请号：US417

申请日：1979-01-02

Applicant: Paul R. Ellis, Jr.

Inventor： Paul R. Ellis, Jr.

IPC: H01R4/02 ,  H01R43/16 ,  H05K1/03 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H05K3/36 ,  H01R13/12

CPC classification number: H05K3/3447 ,  H01R12/718 ,  H01R4/028 ,  H05K3/366 ,  H05K1/0306 ,  H05K2201/10386 ,  H05K2201/10848 ,  H05K2201/10871 ,  H05K2201/2036 ,  H05K2203/308 ,  H05K3/306 ,  H05K3/3468

Abstract: An improved edge clip terminal having a first diamond-shaped transition region connecting a plurality of tines, that clip over the edge of a substrate, to a first lead section and having a second diamond-shaped transition region connecting the first lead section to a second lead section. In an assembly, the second lead sections of a plurality of terminals are located in holes in a PC board with the second transition regions resting on the surface of the circuit board. The first lead sections are more narrow than the transition regions and of lengths that are sufficient for preventing solder wicking up them and into the areas of the tines during wave soldering of a circuit board so that a leaded substrate soldered into the circuit board may be tilted without damaging it. In an alternate embodiment of this invention, the lead portion of an edge clip terminal on a substrate has a pair of spaced apart transition regions in it. A first transition region and first length of lead space tines away from a second transition region in a hole in a circuit board for preventing solder wicking up the lead and tines during wave soldering so that the leaded substrate may be tilted without damaging it.

Abstract translation: 一种改进的边缘夹子端子，其具有连接多个尖端的第一菱形过渡区域，该多个尖端夹在衬底的边缘上，到第一引线部分，并且具有将第一引线部分连接到第二引线部分的第二菱形过渡区域 导线部分。 在组件中，多个端子的第二引线部分位于PC板中的孔中，其中第二过渡区域搁置在电路板的表面上。 第一引线部分比过渡区域和长度足够窄，足以防止焊料在电路板的波峰焊接过程中漏起并进入尖端区域，使得焊接到电路板中的引线基板可能倾斜 而不损坏它。 在本发明的替代实施例中，衬底上边缘夹子端子的引线部分在其中具有一对间隔开的过渡区域。 第一过渡区域和引线空间的第一长度离开电路板上的孔中的第二过渡区域，以防止在波峰焊接过程中焊锡引起铅尖和尖峰，使得引线基板可以倾斜而不损坏引线。

公开(公告)号：US3864014A

公开(公告)日：1975-02-04

申请号：US36880873

申请日：1973-06-11

Applicant: AMP INC

Inventor： LYNCH JAMES EDWARD

IPC: H01R4/02 ,  H05K3/34 ,  H01R5/04

CPC classification number: H01R12/58 ,  H01R4/02 ,  H05K3/3447 ,  H05K2201/1081 ,  H05K2201/10848 ,  H05K2201/10984

Abstract: A connector post or pin is disclosed which is particularly suitable for use with printed circuit board assemblies. The post includes a coined portion which is designed to permit the pin to be easily inserted into holes of a predetermined size in printed circuit boards, and to increase the quality of a solder joint between the post and the printed circuit board. A solder stripe is placed on each post in the coined region to facilitate soldering of the posts to conductive portions of the printed circuit board. The posts are attached in groups to break-away carrier strips to aid in the rapid assembly of large numbers of posts to printed circuit boards. The posts may also include provisions for coupling them to multilayered printed circuit assemblies. A method of fabricating the coined post is also disclosed which converts a post with normally an interference fit in a printed circuit board aperture to a post which is freely received in the aperture together with masses of solder adhered to said post.

Abstract translation: 公开了一种连接器柱或销，其特别适用于印刷电路板组件。 该柱包括设计成允许销易于插入到印刷电路板中的预定尺寸的孔中的模制部分，并且提高柱和印刷电路板之间的焊接接头的质量。 在打印区域中的每个柱上放置焊料条以便于将柱焊接到印刷电路板的导电部分。 这些柱子分组连接以分离载体条，以帮助将大量柱体快速组装到印刷电路板上。 柱子还可以包括用于将它们耦合到多层印刷电路组件的规定。 还公开了一种制造造型柱的方法，其将通常在印刷电路板孔中的过盈配合的柱转换成自由接收在孔中的柱以及粘附到所述柱的焊料块。

公开(公告)号：US20140131307A1

公开(公告)日：2014-05-15

申请号：US13936936

申请日：2013-07-08

Applicant: General Dynamics Advanced Information Systems, Inc.

Inventor： Deepak Keshav Pai ,  Melvin Eric Graf

IPC: H05K3/02

CPC classification number: H01L21/4821 ,  B23K26/361 ,  B23K26/362 ,  H01L21/50 ,  H01L23/49541 ,  H01L23/49548 ,  H01L2924/0002 ,  H05K3/3426 ,  H05K2201/10848 ,  H01L2924/00

Abstract: An embodiment of the invention generally relates to a method of converting a commercial off-the-shelf electrical lead to a rugged off-the-shelf electrical lead by laser machining a portion of the electrical lead. The method includes ablating material from the electrical lead of the commercial off-the-shelf component to reduce the moment of inertia or increase the flexibility of the electrical lead.

Abstract translation: 本发明的一个实施方案一般涉及通过激光加工一部分电引线将商业现货电导线转换成坚固的现成的电引线的方法。 该方法包括从商业现成部件的电引线上烧掉材料以减少转动惯量或增加电引线的灵活性。

公开(公告)号：US20130301231A1

公开(公告)日：2013-11-14

申请号：US13870108

申请日：2013-04-25

Applicant: Valeo Systemes de Controle Moteur

Inventor： Bruno Lefevre ,  Christian Schwartz ,  Jean-Yves Moreno

IPC: H05K13/00 ,  H05K1/18 ,  B23K3/047

CPC classification number: H05K13/00 ,  B23K3/047 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/3494 ,  H05K13/0465 ,  H05K2201/10515 ,  H05K2201/10848 ,  H05K2203/1115 ,  H05K2203/1476 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/53174

Abstract: A production line for producing electronic modules including a printed-circuit board, at least one first-type component, and at least one second-type component, wherein the production line includes a unit for putting the first-type component in place, a general heating unit for melting a solder placed between the at least one first-type component and the circuit, a unit for putting the second-type component in place, and a local heating unit for melting a solder placed between the at least one second-type component and the circuit.

Abstract translation: 一种用于生产包括印刷电路板，至少一个第一类型部件和至少一个第二类型部件的电子模块的生产线，其中生产线包括用于将第一类型部件放置在适当位置的单元， 用于熔化放置在所述至少一个第一类型部件和所述电路之间的焊料的加热单元，用于将所述第二类型部件放置在适当位置的单元和用于熔化置于所述至少一个第二类型部件之间的焊料的局部加热单元 组件和电路。