公开(公告)号：US09198283B2

公开(公告)日：2015-11-24

申请号：US14198658

申请日：2014-03-06

Applicant: Carolyn Rae Ellinger

Inventor： Carolyn Rae Ellinger

IPC: H05K1/16 ,  H05K1/02 ,  H05K1/09

CPC classification number: H05K1/0284 ,  C23C16/345 ,  C23C16/403 ,  C23C16/405 ,  C23C16/407 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2924/0002 ,  H05K1/09 ,  H05K2201/0137 ,  H05K2201/0326 ,  H05K2201/09045 ,  H01L2924/00

Abstract: A vertically separated electrode structure includes a polymeric material post on a substrate. An inorganic material cap covers the top of the post and extends beyond an edge of the post in at least a width dimension to define a first reentrant profile. A first electrode is located over the cap. A second electrode is located over the substrate and not over the post. The second electrode is adjacent to the edge of the post in the reentrant profile such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface. The first electrode and second electrode have the same material composition and layer thickness.

Abstract translation: 垂直分离的电极结构包括在基底上的聚合物材料柱。 无机材料盖覆盖柱的顶部并且在至少一个宽度尺寸上延伸超出柱的边缘以限定第一凹槽轮廓。 第一电极位于盖上。 第二电极位于衬底上并且不在柱上。 第二电极在折返轮廓中与柱的边缘相邻，使得当与衬底表面正交测量时，第一电极和第二电极之间的距离大于零。 第一电极和第二电极具有相同的材料组成和层厚度。

公开(公告)号：US20150207541A1

公开(公告)日：2015-07-23

申请号：US14408797

申请日：2013-06-21

Applicant: KEIO UNIVERSITY

Inventor： Tadahiro Kuroda

IPC: H04B5/00 ,  H04B3/32

CPC classification number: H04B5/0018 ,  H04B3/32 ,  H04B5/0012 ,  H04B5/0031 ,  H04B5/0075 ,  H04B5/0093 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/141 ,  H05K1/147 ,  H05K2201/042 ,  H05K2201/09045

Abstract: The invention relates to a directional coupling communication apparatus where the coupling impedance can be easily matched to reduce reflections, and thus, the speed of communication channels is increased as compared to that with inductive coupling, and at the same time, the reliability of communication is improved by increasing the signal intensity. Modules having a coupler where an input/output connection line is connected to a first end, and either a ground line or an input/output connection line to which an inverse signal of a signal to be inputted into the input/output connection line connected to the above-described first end is inputted is connected are layered on top of each other so that the couplers are couplers to each other using capacitive coupling and inductive coupling.

Abstract translation: 本发明涉及一种方向耦合通信装置，其中耦合阻抗可以容易地匹配以减少反射，因此与电感耦合相比，通信信道的速度增加，同时通信的可靠性是 通过增加信号强度得到改善。 具有耦合器的模块，其中输入/输出连接线连接到第一端，以及接地线或输入/输出连接线，要输入到输入/输出连接线的信号的反相信号连接到 输入的上述第一端被连接成层叠在彼此的顶部上，使得耦合器使用电容耦合和电感耦合彼此耦合。

公开(公告)号：US20150181690A1

公开(公告)日：2015-06-25

申请号：US14516487

申请日：2014-10-16

Applicant: HYUNDAI MOTOR COMPANY ,  KIA MOTORS CORPORATION ,  YURA CORPORATION CO., LTD.

Inventor： Mun Jong KIM ,  Kwan Bum LEE ,  Jin Su YEOM

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/44 ,  H05K3/46 ,  H05K3/00 ,  H05K3/06

CPC classification number: H05K1/0201 ,  H05K1/0206 ,  H05K1/09 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/067 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0338 ,  H05K2201/09045 ,  H05K2203/0278 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: A heat dissipation printed circuit board includes a metal core, lower and upper insulating layers, first lower and first upper circuit patterns, and second lower and second upper circuit patterns. The lower and upper insulating layers are disposed at a lower side and an upper side of the metal core, respectively. The first lower and first upper circuit patterns are disposed at a lower side of the lower insulating layer and at an upper side of the upper insulating layer, respectively. The second lower and second upper circuit patterns are disposed at a lower side of the first lower circuit pattern and at an upper side of the first upper circuit pattern, respectively. An etching portion in the first lower circuit pattern is filled with the lower insulating layer and an etching portion in the first upper circuit pattern is filled with the upper insulating layer.

Abstract translation: 散热印刷电路板包括金属芯，下绝缘层和上绝缘层，第一下电极图案和第一上电路图案以及第二下电路图案和第二上电路图案。 下绝缘层和上绝缘层分别设置在金属芯的下侧和上侧。 第一下电极和第一上电路图案分别设置在下绝缘层的下侧和上绝缘层的上侧。 第二下电路图案和第二上电路图案分别设置在第一下电路图案的下侧和第一上电路图案的上侧。 第一下部电路图案中的蚀刻部分填充有下部绝缘层，并且第一上部电路图案中的蚀刻部分填充有上部绝缘层。

公开(公告)号：US20150009645A1

公开(公告)日：2015-01-08

申请号：US14308853

申请日：2014-06-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kentaro KANEKO ,  Katsuya FUKASE

IPC: H05K1/11

CPC classification number: H05K3/4682 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H05K1/112 ,  H05K1/113 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/381 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/2072 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/1184 ,  H05K2203/308

Abstract: A wiring substrate includes an insulating layer that is an outermost layer of the wiring substrate and includes an external exposed surface, a pad forming part formed on a side of the external exposed surface, and a pad that projects from the external exposed surface. The pad forming part includes a recess part recessed from the external exposed surface, and a weir part that projects from the external exposed surface and encompasses the recess part from a plan view. The pad includes a pad body formed within the recess part and the weir part, and an eave part formed on the weir part. The pad body includes an end part that projects to the weir part. The eave part projects in a horizontal direction from the end part of the pad body. The end part of the pad body includes a flat surface.

Abstract translation: 布线基板包括绝缘层，其是布线基板的最外层，并且包括外部暴露表面，形成在外部暴露表面侧的焊盘形成部分以及从外部暴露表面突出的焊盘。 衬垫形成部分包括从外部暴露表面凹陷的凹陷部分和从外部暴露表面突出并从俯视图包围凹部的堰部分。 衬垫包括形成在凹部和堰部内的垫体，以及形成在堰部上的檐部。 垫体包括突出到堰部分的端部。 檐部从垫体的端部沿水平方向突出。 垫体的端部包括平坦表面。

公开(公告)号：US20140361437A1

公开(公告)日：2014-12-11

申请号：US14082289

申请日：2013-11-18

Applicant: SK hynix Inc.

Inventor： Hyun Chul SEO ,  Jong Hoon KIM ,  Jae Woong YU

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/4846 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  H01L2924/00

Abstract: Package substrates are provided. The package substrate includes a core layer having a first surface defining trench portions and ridge portions between the trench portions, at least one first trace on a bottom surface of each of the trench portions, and second traces on respective ones of top surfaces of the ridge portions. Related methods are also provided.

Abstract translation: 提供封装衬底。 封装衬底包括芯层，其具有第一表面，第一表面限定沟槽部分和沟槽部分之间的脊部分，每个沟槽部分的底表面上的至少一个第一迹线以及脊部的各个顶表面上的第二迹线 部分。 还提供了相关方法。

公开(公告)号：US20140305686A1

公开(公告)日：2014-10-16

申请号：US14246266

申请日：2014-04-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiromichi KITAJIMA

IPC: H05K1/18

CPC classification number: H05K1/0298 ,  H01L2224/16225 ,  H01L2924/15174 ,  H05K3/341 ,  H05K3/4629 ,  H05K2201/0352 ,  H05K2201/09045 ,  H05K2201/09672

Abstract: A multilayer wiring substrate includes a multilayer body in which a plurality of insulating layers is stacked and to which an electronic component is mounted, a plurality of connection terminals disposed on one principal surface of the multilayer body for connection to the electronic component, and a plurality of rear electrodes disposed on the other principal surface of the multilayer body, wherein the connection terminals are each arranged in overlapped relation to one of the rear electrodes when looked at in a plan view of the multilayer wiring substrate.

Abstract translation: 多层布线基板包括堆叠多个绝缘层并且安装电子部件的多层体，设置在多层体的一个主面上的多个连接端子，用于与电子部件连接，多个连接端子 设置在所述多层体的另一主面上的后电极，其中，当在所述多层布线基板的俯视图中观察时，所述连接端子与所述后电极中的一个重叠地布置。

公开(公告)号：US08698186B2

公开(公告)日：2014-04-15

申请号：US13186461

申请日：2011-07-19

Applicant: Lac Nguyen ,  Chang Han

Inventor： Lac Nguyen ,  Chang Han

IPC: H01L33/62

CPC classification number: H05K1/0203 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/48091 ,  H05K1/0204 ,  H05K1/0306 ,  H05K1/05 ,  H05K2201/0385 ,  H05K2201/09045 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2201/10416 ,  H05K2201/10969 ,  H01L2924/00014

Abstract: An LED device with improved circuit board LED support structure is presented. A top surface of a thermally-conductive substrate of this LED device comprises a thermally-conductive pillar. The pillar is not covered with a dielectric layer and an LED package is arranged directly on the pillar with the LED packages bottom thermally-conductive plate in direct contact with the pillar top surface.

Abstract translation: 提出了一种具有改进的电路板LED支撑结构的LED器件。 该LED装置的导热基板的顶面包括导热柱。 柱子不被电介质层覆盖，并且LED封装直接布置在柱上，LED封装底部导热板与柱顶表面直接接触。

公开(公告)号：US20140003015A1

公开(公告)日：2014-01-02

申请号：US14016707

申请日：2013-09-03

Applicant: Shinji WATANABE ,  Nobuhiro MIKAMI ,  Junya SATO ,  Kenichiro FUJII ,  Katsumi ABE ,  Atsumasa SAWADA

Inventor： Shinji WATANABE ,  Nobuhiro MIKAMI ,  Junya SATO ,  Kenichiro FUJII ,  Katsumi ABE ,  Atsumasa SAWADA

IPC: H05K1/18

CPC classification number: H05K1/18 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1515 ,  H01L2924/15151 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/023 ,  H05K1/0271 ,  H05K1/0284 ,  H05K1/185 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/32 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09436 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2203/1469 ,  H05K2203/302 ,  Y02P70/611 ,  H01L2924/00

Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.

Abstract translation: 本发明的目的在于，当将半导体封装安装在弯曲的基板上时，可以抑制对半导体封装件施加的应力。 在安装基板1中，将半导体封装20安装在其至少一部分上包括弯曲表面的弯曲板10上。 弯曲板10包括设置在半导体封装20安装的弯曲表面部分的区域上并具有平坦的上表面的基座部分13a和设置在基座部分的平坦表面上的多个焊盘部分15a 13a。 基座部分13a由绝缘材料形成。 半导体封装20安装在焊盘部分15a上。

公开(公告)号：US08541093B2

公开(公告)日：2013-09-24

申请号：US13354159

申请日：2012-01-19

Applicant: Tae-Su Kim ,  Jae-Jin Kim ,  Bu-Gon Shin ,  Duk-Sik Ha ,  Jung-Ho Park

Inventor： Tae-Su Kim ,  Jae-Jin Kim ,  Bu-Gon Shin ,  Duk-Sik Ha ,  Jung-Ho Park

IPC: G02F1/1335

CPC classification number: H05K3/125 ,  H05K3/107 ,  H05K3/1208 ,  H05K3/1258 ,  H05K3/381 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/2072 ,  H05K2203/013 ,  Y10T428/24355 ,  Y10T428/24521 ,  Y10T428/24537 ,  Y10T428/24545 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/2462 ,  Y10T428/24669 ,  Y10T428/24694 ,  Y10T428/24802

Abstract: A method for high resolution ink-jet print using a pre-patterned substrate employs an ink-jet printing device including an ink-jet head for discharging conductive ink droplets and a driving stage for supporting a substrate to which the conductive ink droplets are hit, to draw a fine line width pattern on the substrate. The method includes (A) forming a stripe pattern with repeated stripes on a substrate surface on which a fine line width pattern will be formed, thereby preparing a pre-patterned substrate; (B) loading the substrate to the ink-jet printing device; and (C) injecting conductive ink droplets to a substrate region where the stripe pattern is formed. An equivalent interval (d) of the stripe pattern and a fine line width (D) of the drawn fine line width pattern satisfy a relation of d

Abstract translation: 使用预图案化基板的高分辨率喷墨打印方法采用喷墨打印装置，其包括用于排放导电墨滴的喷墨头和用于支撑导电墨滴撞击的基板的驱动台， 以在衬底上画出细线宽度图案。 该方法包括：（A）在其上将形成细线宽度图案的基板表面上形成具有重复条纹的条纹图案，从而制备预图案化基板; （B）将基板装载到喷墨打印装置; 和（C）将导电墨滴注入形成条纹图案的基片区域。 条形图案的等效间隔（d）和所绘制的细线宽度图案的细线宽度（D）满足d << D的关系，并且所击中的墨滴以该区域内的各向异性形式流动。

公开(公告)号：US08445831B2

公开(公告)日：2013-05-21

申请号：US13302907

申请日：2011-11-22

Applicant: Rick Lake ,  Ulrich Boettiger ,  Shashikant Hegde ,  Jacques Duparre

Inventor： Rick Lake ,  Ulrich Boettiger ,  Shashikant Hegde ,  Jacques Duparre

IPC: H01L27/00 ,  H01L23/48

CPC classification number: H01L24/16 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/351 ,  H05K3/32 ,  H05K3/4007 ,  H05K2201/09045 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Various embodiments include interconnects for semiconductor structures that can include a first conductive structure, a second conductive structure and a non-hardening liquid conductive material in contact with the first and second structure. Other embodiments include semiconductor components and imager devices using the interconnects. Further embodiments include methods of forming a semiconductor structure and focusing methods for an imager device.

Abstract translation: 各种实施例包括用于半导体结构的互连，其可以包括与第一和第二结构接触的第一导电结构，第二导电结构和非硬化液体导电材料。 其他实施例包括使用互连的半导体部件和成像器件。 另外的实施例包括形成半导体结构的方法和用于成像器装置的聚焦方法。