中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

741 records (took 0.023 seconds)

    Using time-domain reflectometry to identify manufacturing information for a passive printed circuit board
    21.
    发明授权
    Using time-domain reflectometry to identify manufacturing information for a passive printed circuit board 有权
    使用时域反射法识别被动印刷电路板的制造信息

    公开(公告)号：US09310417B2

    公开(公告)日：2016-04-12

    申请号：US14036712

    申请日：2013-09-25

    Applicant: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.

    Inventor： Jordan HP Chin ,  Timothy M. Wiwel

    IPC: G01R31/11 ,  H05K3/10 ,  G01R31/28 ,  H05K3/00 ,  H05K1/02

    CPC classification number: G01R31/11 ,  G01R31/2805 ,  G01R31/2818 ,  H05K1/0248 ,  H05K1/0268 ,  H05K3/0047 ,  H05K2201/09263 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2203/163 ,  H05K2203/171 ,  H05K2203/175 ,  Y10T29/49155

    Abstract: A method uses time-domain reflectometry to measure a signal reflection delay in a conductive trace formed on a specific passive printed circuit board, and uses the measured signal reflection delay as an index into a table storing a predetermined association between signal reflection delay and passive printed circuit board manufacturing information, wherein the table includes a plurality of predetermined signal reflection delay values, and wherein each of the predetermined signal reflection delay values is associated with unique passive printed circuit board manufacturing information. During manufacturing of the passive printed circuit board, a hole is drilled through the passive printed circuit board so that the hole intersects with the conductive trace and divides the conductive trace into a proximal segment extending from the connector to the hole and a distal segment that is electrically isolated from the proximal segment by the hole.

    Abstract translation: 一种方法使用时域反射测量来测量在特定无源印刷电路板上形成的导电迹线中的信号反射延迟，并且使用测量的信号反射延迟作为索引，存储在信号反射延迟和被动印刷之间的预定关联 电路板制造信息，其中所述表包括多个预定信号反射延迟值，并且其中每个预定信号反射延迟值与唯一的被动印刷电路板制造信息相关联。 在无源印刷电路板的制造期间，通过无源印刷电路板钻出孔，使得孔与导电迹线相交，并将导电迹线分成从连接器延伸到孔的近端段，以及远端段 通过孔与近端段电隔离。

    Flexible circuit board
    22.
    发明授权
    Flexible circuit board 有权
    柔性电路板

    公开(公告)号：US09270001B2

    公开(公告)日：2016-02-23

    申请号：US13935132

    申请日：2013-07-03

    Applicant: Sumitomo Electric Device Innovations, Inc.

    Inventor： Masahiro Hirayama

    IPC: G02B6/36 ,  H01P3/02 ,  G02B6/42 ,  H05K1/02 ,  H05K1/11

    CPC classification number: H01P3/026 ,  G02B6/4279 ,  G02B6/4281 ,  G02B6/4292 ,  H05K1/0219 ,  H05K1/0227 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/117 ,  H05K2201/09181 ,  H05K2201/09236 ,  H05K2201/09618 ,  H05K2201/0969

    Abstract: A flexible circuit board includes: an insulative substrate having a first surface and a second surface opposite to the first surface; a microstrip line having a first signal line formed on the first surface and a first ground pattern formed on the second surface and located in an area opposite to the first signal line; a coplanar line having a second signal line formed on the first surface, and second ground patterns that are formed on the first surface and are spaced apart from both sides of the second signal line; a connection line that is formed on the first surface and connects the first signal line and the second signal line together, the connection line having an opening; and third ground patterns formed on the second surface and arranged in areas located at both sides of an area opposite to the connection line including the opening.

    Abstract translation: 柔性电路板包括：具有第一表面和与第一表面相对的第二表面的绝缘基板; 具有形成在第一表面上的第一信号线和形成在第二表面上并位于与第一信号线相对的区域中的第一接地图案​​的微带线; 具有形成在第一表面上的第二信号线的共面线和形成在第一表面上并与第二信号线的两侧隔开的第二接地图案; 连接线，其形成在所述第一表面上并将所述第一信号线和所述第二信号线连接在一起，所述连接线具有开口; 以及形成在第二表面上并且布置在位于与包括开口的连接线相对的区域的两侧的区域中的第三接地图案。

    Structure for Isolating High Speed Digital Signals in a High Density Grid Array
    23.
    发明申请
    Structure for Isolating High Speed Digital Signals in a High Density Grid Array 审中-公开
    在高密度网格阵列中隔离高速数字信号的结构

    公开(公告)号：US20150348901A1

    公开(公告)日：2015-12-03

    申请号：US14721263

    申请日：2015-05-26

    Applicant: Thomas P. Warwick

    Inventor： Thomas P. Warwick

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H01L23/5225 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L2224/16225 ,  H05K1/0222 ,  H05K1/0243 ,  H05K1/113 ,  H05K1/116 ,  H05K2201/0723 ,  H05K2201/09227 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K2201/10674 ,  H05K2203/0207

    Abstract: Due to size and cost, it becomes advantageous for integrated circuit (IC) manufacturers to use “single-ended” (one signal path per unique information path) high speed signals electrical contact pins (pins transmitting digital information that connect the integrated circuit to a printed circuit board) with a minimum number of surrounding powers and grounds. This lower cost method, however, creates electrical interference and coupling issues known as crosstalk between two adjacent signal paths in the via structure required to electrically connect the integrated circuit to the signal paths in the printed circuit board. Such crosstalk, in turn, increases jitter, degrades timing, and ultimately reduces the maximum operating speed of the circuit (performance). This disclosure presents a structure using micro-plating, micro-drilling and micro-machining methods that isolates adjacent signals by placing a metal barrier that shunts coupling currents to ground. The micro-drilling methods also reduce the length of adjacent signal paths in a specific signal routing and controlled depth drilling sequence.

    Abstract translation: 由于尺寸和成本，集成电路（IC）制造商使用“单端”（每个唯一信息路径的一个信号路径）高速信号电接触引脚（引脚将数字信息连接到集成电路 印刷电路板），具有最小数量的周围电源和接地。 然而，这种较低成本的方法在将集成电路电连接到印刷电路板中的信号路径所需的通孔结构中产生称为串扰的两个相邻信号路径之间的电干扰和耦合问题。 这种串扰又增加抖动，降低定时，并最终降低电路的最大工作速度（性能）。 本公开提供了使用微电镀，微钻孔和微加工方法的结构，其通过放置将耦合电流分流到地面的金属屏障来隔离相邻信号。 微钻孔方法还可以减小特定信号路由和受控深度钻井序列中相邻信号路径的长度。

    Electromagnetic interference shielding techniques
    25.
    发明授权
    Electromagnetic interference shielding techniques 有权
    电磁干扰屏蔽技术

    公开(公告)号：US09155188B2

    公开(公告)日：2015-10-06

    申请号：US13631156

    申请日：2012-09-28

    Applicant: Apple Inc.

    Inventor： Nicholas G. Merz ,  Hong Wang ,  Michael M. Nikkhoo ,  Dennis R. Pyper ,  Christopher Matthew Werner

    IPC: H05K9/00 ,  H05K1/02 ,  H05K3/28

    CPC classification number: H05K1/0218 ,  H05K3/284 ,  H05K2201/0317 ,  H05K2201/09618 ,  H05K2201/09872 ,  H05K2201/09909 ,  H05K2201/10371 ,  H05K2201/2018 ,  Y10T29/4913 ,  Y10T29/49146

    Abstract: Methods and apparatuses are disclosed for fabricating a printed circuit board (PCB) having electromagnetic interference (EMI) shielding and also having reduced volume over conventional frame-and-shield approaches. Some embodiments include fabricating the PCB by mounting an integrated circuit to the PCB, outlining an area corresponding to the integrated circuit with a number of grounded vias, selectively applying an insulating layer over the PCB such that at least one of the grounded vias are exposed, and selectively applying a conductive layer over the PCB such that the conductive layer covers at least a portion of the integrated circuit and such that the conductive layer is coupled to the at least one of the grounded vias that are exposed.

    Abstract translation: 公开了用于制造具有电磁干扰（EMI）屏蔽的印刷电路板（PCB）的方法和装置，并且与传统的框架 - 屏蔽方法相比也具有减小的体积。 一些实施例包括通过将集成电路安装到PCB来制造PCB，通过多个接地通孔来概括对应于集成电路的区域，在PCB上选择性地施加绝缘层，使得接地通孔中的至少一个暴露， 以及选择性地在所述PCB上施加导电层，使得所述导电层覆盖所述集成电路的至少一部分，并且使得所述导电层耦合到暴露的所述接地通孔中的至少一个。

    High-frequency circuit package and sensor module
    26.
    发明授权
    High-frequency circuit package and sensor module 有权
    高频电路封装和传感器模块

    公开(公告)号：US09070961B2

    公开(公告)日：2015-06-30

    申请号：US13062349

    申请日：2009-09-02

    Applicant: Takuya Suzuki

    Inventor： Takuya Suzuki

    IPC: H05K1/11 ,  H05K1/14 ,  H01P5/107 ,  H01L23/552 ,  H01L23/58 ,  H01L23/66 ,  H01L25/18 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H05K3/34

    CPC classification number: H05K1/0218 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/552 ,  H01L23/585 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/18 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2225/0652 ,  H01L2924/15321 ,  H01L2924/1903 ,  H01L2924/19032 ,  H01L2924/3011 ,  H01P3/081 ,  H01P5/107 ,  H01Q9/04 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/0243 ,  H05K3/3436 ,  H05K2201/09618 ,  H05K2201/10151 ,  H05K2201/10734

    Abstract: Shielding of high-frequency circuits is achieved using a simple and inexpensive configuration not using any lid. A high-frequency circuit mounting substrate (20) is disposed, on an underside surface layer of which are disposed high-frequency circuits (21 and 22) and is formed a first grounding conductor that has same electric potential as grounding conductors of the high-frequency circuits and that surrounds the high-frequency circuits. A mother control substrate (3) is disposed, on which the high-frequency circuit mounting substrate (20) is mounted in such a way that the high-frequency circuits are sandwiched therebetween and on which a second grounding conductor is formed in a region facing the high-frequency circuits. Plural first lands are formed on the first grounding conductor of the high-frequency circuit mounting substrate (20) to surround the high-frequency circuits. Plural second lands are formed that are electrically connected to the second grounding conductor at positions on a surface layer of the mother control substrate (3) which face the first lands. Plural solder balls (30G2) are disposed for connecting the first lands and the second lands. The high-frequency circuits are housed in pseudo shielding cavities surrounded by the solder balls (30G2), the grounding conductors of the high-frequency circuits, and the first and second grounding conductors.

    Abstract translation: 使用不使用任何盖子的简单且便宜的配置来实现高频电路的屏蔽。 高频电路安装基板（20）设置在其下表面层上，设置有高频电路（21和22），并形成与第一接地导体相同的电位的第一接地导体， 频率电路，并且围绕高频电路。 设置母控制基板（3），其上安装有高频电路安装基板（20），使得高频电路夹在其间并在其上形成有第二接地导体的区域 高频电路。 多个第一焊盘形成在高频电路安装基板（20）的第一接地导体上，以围绕高频电路。 形成在母板控制基板（3）的面对第一焊盘的位置处与第二接地导体电连接的多个第二焊盘。 多个焊球（30G2）被设置用于连接第一焊盘和第二焊盘。 高频电路容纳在由焊球（30G2），高频电路的接地导体以及第一和第二接地导体包围的伪屏蔽腔中。

    Via Layout Techniques for Improved Low Current Measurements
    28.
    发明申请
    Via Layout Techniques for Improved Low Current Measurements 有权
    通过布局技术改进低电流测量

    公开(公告)号：US20150168463A1

    公开(公告)日：2015-06-18

    申请号：US14133167

    申请日：2013-12-18

    Applicant: NATIONAL INSTRUMENTS CORPORATION

    Inventor： John G. Banaska ,  Pablo Limon

    IPC: G01R19/00 ,  H05K1/11 ,  H05K3/30 ,  G01R31/28

    CPC classification number: G01R19/0092 ,  G01R3/00 ,  H05K1/0219 ,  H05K1/0268 ,  H05K2201/09618 ,  Y10T29/49147

    Abstract: System and methods for use and fabrication of a printed circuit board (PCB). The PCB may include a node and a plurality of rows of vias that may be configured to establish a plurality of current pathways away from the node. The node may be a sensitive node and the plurality of current pathways may reduce leakage current at the node responsive to a signal applied to the node. Each row of the plurality of rows of vias may be offset with respect to adjacent rows of vias in a horizontal plane of the PCB. The PCB may have multiple layers and the node may be on an exterior surface layer or an interior layer. The vias may be mirco-vias, buried-vias, or through-vias.

    Abstract translation: 印刷电路板（PCB）的使用和制造的系统和方法。 PCB可以包括可以被配置为建立远离节点的多个电流路径的节点和多个通孔行。 节点可以是敏感节点，并且多个当前路径可以响应于施加到节点的信号来减少节点处的泄漏电流。 多行通孔中的每一行可以相对于PCB的水平平面中的相邻的通孔行而偏移。 PCB可以具有多个层，并且节点可以在外表面层或内层上。 通孔可以是通孔，通孔或通孔。

Patent Agency Ranking