公开(公告)号：US20130251978A1

公开(公告)日：2013-09-26

申请号：US13847457

申请日：2013-03-19

Applicant: IMEC ,  ST. PETERSBURG ELECTROTECHNICAL UNIVERSITY

Inventor： Victor Luchinin ,  Svetlana Goloudina ,  Vyacheslav Pasyuta ,  Alexey Ivanov ,  Mikhail Baklanov ,  Mikhail Krishtab

IPC: B32B37/15

CPC classification number: B32B37/15 ,  B05D1/20 ,  B05D1/208 ,  B32B18/00 ,  B32B27/04 ,  B32B27/281 ,  B32B2260/046 ,  B32B2305/026 ,  B32B2305/07 ,  B32B2307/00 ,  B32B2307/204 ,  B32B2379/08 ,  B32B2457/00 ,  C08G73/1067 ,  C09D179/08 ,  H01L21/02285 ,  H01L21/02318 ,  H05K1/03 ,  H05K3/143 ,  H05K2201/01 ,  H05K2201/0104 ,  H05K2201/0116 ,  H05K2201/0154 ,  H05K2201/0162 ,  Y10T428/249979 ,  Y10T428/249991 ,  C08K5/175

Abstract: Method for pore sealing a porous substrate, comprising: forming a continuous monolayer of a polyimide precursor on a liquid surface, transferring said polyimide precursor monolayer onto the porous substrate with the Langmuir-Blodgett technique, and imidization of the transferred polyimide precursor monolayers, thereby forming a polyimide sealing layer on the porous substrate. Porous substrate having at least one surface on which a sealing layer is provided to seal pores of the substrate, wherein the sealing layer is a polyimide having a thickness of a few monolayers and wherein there is no penetration of the polyimide into the pores.

Abstract translation: 用于孔密封多孔基材的方法，包括：在液体表面上形成聚酰亚胺前体的连续单层，使用Langmuir-Blodgett技术将所述聚酰亚胺前体单层转移到多孔基材上，并将转移的聚酰亚胺前体单层酰亚胺化，从而形成 多孔基材上的聚酰亚胺密封层。 具有至少一个表面的多孔基材，其上设有密封层以密封基材的孔，其中密封层是具有几个单层厚度的聚酰亚胺，并且其中聚酰亚胺不渗透到孔中。

公开(公告)号：US20240206050A1

公开(公告)日：2024-06-20

申请号：US18422117

申请日：2024-01-25

Applicant: Wuhan Tianma Microelectronics Co., Ltd. ,  Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch

Inventor： Xuejing XIAO ,  Zhenzhen XIE

IPC: H05K1/02 ,  H05K1/18 ,  H05K5/02

CPC classification number: H05K1/0269 ,  H05K5/02 ,  H05K1/181 ,  H05K2201/0104 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10159

Abstract: Provided is a circuit board and an electronic device thereof. The circuit board includes: a substrate; an insulating ink layer disposed on the substrate; a component disposed on a side of the insulating ink layer facing away from the substrate, where the component is electrically connected to the substrate through a window opening area on the substrate; and an encapsulation layer disposed on a side of the component facing away from the substrate. The insulating ink layer includes a first hydrochromic material, and in a case where humidity exceeds a first humidity threshold, the first hydrochromic material changes from a first color to a second color.

公开(公告)号：US20240074127A1

公开(公告)日：2024-02-29

申请号：US18221461

申请日：2023-07-13

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chen-Yu Wang ,  Pai-Sheng Cheng ,  Huan-Kuen Chen

IPC: H05K9/00 ,  H05K1/05 ,  H05K1/18

CPC classification number: H05K9/0037 ,  H05K1/05 ,  H05K1/181 ,  H05K9/0088 ,  H05K2201/0104 ,  H05K2201/10977

Abstract: In a method of manufacturing an electronic package, first grooves are formed on a circuit structure and a second groove is formed in each of the first grooves to allow the circuit structure to become circuit layers. Owing to the second groove is narrower than the first groove, each of the circuit layers has an encircled surface and a notch located on the encircled surface. When a shielding layer is provided to cover an encapsulating body located on the circuit layer, a space of the notch is not covered by the shielding layer such that a portion to be removed of the shielding layer will not remain on the electronic package to become burr after removing the portion to be removed.

公开(公告)号：US20180110149A1

公开(公告)日：2018-04-19

申请号：US15559975

申请日：2016-03-23

Applicant: SAFRAN ELECTRONICS & DEFENSE

Inventor： Francois GUILLOT ,  Pascal SPOOR ,  Patrice CHETANNEAU

IPC: H05K7/14 ,  G06F1/18 ,  H05K1/11 ,  H05K3/46 ,  H05K3/00 ,  H05K3/42 ,  H01R12/70 ,  H01R12/71

CPC classification number: H05K7/1439 ,  G06F1/184 ,  H01R12/7064 ,  H01R12/716 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/0094 ,  H05K3/421 ,  H05K3/4644 ,  H05K7/1412 ,  H05K7/1445 ,  H05K7/1452 ,  H05K7/1459 ,  H05K2201/0104 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/10189 ,  H05K2201/10295

Abstract: The present invention concerns a backplane electronic board (20) having on inner face (142) suitable for bein g connected to electronic board connectors (12) and an outer face (143) suitable for being connected lo an outer connector (15), the backplane board (20) being characterised in that it has blind holes opening on ihe inner face (142) of some, and holes opening on the outer face (143) of same, the holes being suitable for receiving press-fit connection elements and forming therewith an electrical connection point.

公开(公告)号：US20180110127A1

公开(公告)日：2018-04-19

申请号：US15568137

申请日：2016-04-27

Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  UNIVERSITE D'AIX MARSEILLE

Inventor： Anne Patricia Blanche ALLONCLE ,  Philippe Christian Maurice DELAPORTE

IPC: H05K3/12

CPC classification number: H05K3/1275 ,  H05K3/025 ,  H05K3/046 ,  H05K3/10 ,  H05K2201/0104 ,  H05K2201/0257 ,  H05K2203/0528 ,  H05K2203/0736 ,  H05K2203/108 ,  H05K2203/128

Abstract: The invention relates to a laser printing method that includes the following steps: (a) the provision of a receiver substrate (4); (b) the provision of a target substrate (5) comprising a transparent substrate (50) one surface of which has a coating has a coating (51) constituted of a solid metal film; (c) the localised irradiation of the said film (51) through the said transparent substrate (50) by means of a first laser (6) in order to reach the melting temperature of the metal in a target zone of the said film which is in liquid form; (d) the irradiation of the said liquid film through the said transparent substrate by means of a second laser on the said target zone defined in the step (c), in order to form a liquid jet in the said target zone and bring about the ejection thereof from the substrate in the form of molten metal; (e) the depositing on the receiver substrate of a molten metal drop over a defined receiving zone, with the said drop solidifying upon cooling.

公开(公告)号：US09924594B2

公开(公告)日：2018-03-20

申请号：US14499915

申请日：2014-09-29

Applicant: Infineon Technologies AG

Inventor： Andre Arens ,  Juergen Hoegerl ,  Magdalena Hoier

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/11 ,  H01L21/56 ,  H01L25/18 ,  H01L25/00 ,  H05K1/18 ,  H05K1/02 ,  H05K3/28 ,  H05K7/14 ,  H05K1/14 ,  H01L23/31

CPC classification number: H05K1/111 ,  H01L21/56 ,  H01L23/3121 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/13055 ,  H01L2924/181 ,  H05K1/0256 ,  H05K1/144 ,  H05K1/181 ,  H05K3/28 ,  H05K3/284 ,  H05K7/1432 ,  H05K2201/0104 ,  H05K2201/042 ,  H05K2201/10303 ,  H05K2201/10318 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.

公开(公告)号：US20180067581A1

公开(公告)日：2018-03-08

申请号：US15558064

申请日：2016-03-25

Applicant: LG CHEM, LTD.

Inventor： Ilha LEE ,  Ki-Hwan KIM ,  Song Ho JANG ,  Jin Woo PARK ,  Chan Hyoung PARK

IPC: G06F3/044 ,  H05K1/02 ,  H05K3/46 ,  H05K3/06 ,  G06F3/041

CPC classification number: G06F3/044 ,  G02B1/11 ,  G02B1/111 ,  G02F1/133502 ,  G06F3/0412 ,  G06F2203/04103 ,  G06F2203/04112 ,  H05K1/0274 ,  H05K1/028 ,  H05K3/06 ,  H05K3/46 ,  H05K2201/0104 ,  H05K2201/09681 ,  H05K2201/2054

Abstract: The present specification relates to a conductive structure body and a manufacturing method thereof.

公开(公告)号：US20170158807A1

公开(公告)日：2017-06-08

申请号：US15321628

申请日：2015-07-01

Applicant: DIC CORPORATION

Inventor： Yasuyo YOSHIMOTO ,  Hiroshi KINOSHITA

IPC: C08G59/32 ,  C09J163/00 ,  C08K9/08 ,  C08K3/36 ,  C08K3/22 ,  H01L23/00 ,  C08K7/02 ,  H05K1/02 ,  H05K1/03 ,  H01L23/29 ,  H01L23/373 ,  C08G59/50 ,  C09J11/04

CPC classification number: C08G59/3218 ,  C08G59/245 ,  C08G59/32 ,  C08G59/5073 ,  C08K3/00 ,  C08K3/22 ,  C08K3/36 ,  C08K7/02 ,  C08K9/08 ,  C08K2003/2227 ,  C08K2201/001 ,  C08L63/00 ,  C09J9/00 ,  C09J11/04 ,  C09J163/00 ,  H01L23/295 ,  H01L23/3737 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2924/01006 ,  H01L2924/04541 ,  H01L2924/0463 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/0532 ,  H01L2924/0542 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/186 ,  H05K1/0203 ,  H05K1/0373 ,  H05K2201/0104

Abstract: An epoxy resin composition for electronic material, containing a polyfunctional biphenyl type epoxy resin that is a triglycidyloxybiphenyl or a tetraglycidyloxybiphenyl and at least one of a curing agent and a curing accelerator is provided. Furthermore, the epoxy resin composition for electronic material, further containing a filler, in particular, a thermal conductive filler, is provided. Furthermore, a cured product obtained by curing the epoxy resin composition for electronic material, and an electronic component containing the cured product are provided.

公开(公告)号：US20170094810A1

公开(公告)日：2017-03-30

申请号：US15266624

申请日：2016-09-15

Applicant: Semblant Limited

Inventor： Gianfranco Aresta ,  Gareth Hennighan ,  Andrew Simon Hall Brooks ,  Shailendra Vikram Singh

IPC: H05K3/46 ,  C23C16/505 ,  H05K1/18

CPC classification number: H05K3/467 ,  C23C16/30 ,  C23C16/505 ,  H05K1/181 ,  H05K3/285 ,  H05K2201/0104 ,  H05K2201/0162 ,  H05K2201/09872 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10037 ,  H05K2201/10053 ,  H05K2201/10075 ,  H05K2201/10083 ,  H05K2201/10098 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2201/10128 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2201/10181 ,  H05K2203/095 ,  H05K2203/121 ,  H05K2203/1322 ,  H05K2203/1338

Abstract: An electrical assembly which has a multi-layer conformal coating on at least one surface of the electrical assembly, wherein each layer of the multi-layer coating is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O2, N2O, NO2, H2, NH3, N2, SiF4 and/or hexafluoropropylene (HFP), and (c) optionally He, Ar and/or Kr. The chemistry of the resulting plasma-deposited material chemistry can be described by the general formula: SiOxHyCzFaNb. The properties of the conformal coating are tailored by tuning the values of x, y, z, a and b.

公开(公告)号：US09492841B2

公开(公告)日：2016-11-15

申请号：US13847457

申请日：2013-03-19

Applicant: IMEC ,  St. Petersburg Electrotechnical University

Inventor： Victor Luchinin ,  Svetlana Goloudina ,  Vyacheslav Pasyuta ,  Alexey Ivanov ,  Mikhail Baklanov ,  Mikhail Krishtab

IPC: B05D1/20 ,  B32B37/15 ,  B32B18/00 ,  B32B27/04 ,  B32B27/28 ,  H05K1/03 ,  H01L21/02 ,  H05K3/14 ,  C09D179/08 ,  C08G73/10

CPC classification number: B32B37/15 ,  B05D1/20 ,  B05D1/208 ,  B32B18/00 ,  B32B27/04 ,  B32B27/281 ,  B32B2260/046 ,  B32B2305/026 ,  B32B2305/07 ,  B32B2307/00 ,  B32B2307/204 ,  B32B2379/08 ,  B32B2457/00 ,  C08G73/1067 ,  C09D179/08 ,  H01L21/02285 ,  H01L21/02318 ,  H05K1/03 ,  H05K3/143 ,  H05K2201/01 ,  H05K2201/0104 ,  H05K2201/0116 ,  H05K2201/0154 ,  H05K2201/0162 ,  Y10T428/249979 ,  Y10T428/249991 ,  C08K5/175

Abstract: Method for pore sealing a porous substrate, comprising: forming a continuous monolayer of a polyimide precursor on a liquid surface, transferring said polyimide precursor monolayer onto the porous substrate with the Langmuir-Blodgett technique, and imidization of the transferred polyimide precursor monolayers, thereby forming a polyimide sealing layer on the porous substrate. Porous substrate having at least one surface on which a sealing layer is provided to seal pores of the substrate, wherein the sealing layer is a polyimide having a thickness of a few monolayers and wherein there is no penetration of the polyimide into the pores.

Abstract translation: 用于孔密封多孔基材的方法，包括：在液体表面上形成聚酰亚胺前体的连续单层，使用Langmuir-Blodgett技术将所述聚酰亚胺前体单层转移到多孔基材上，并将转移的聚酰亚胺前体单层酰亚胺化，从而形成 多孔基材上的聚酰亚胺密封层。 具有至少一个表面的多孔基材，其上设有密封层以密封基材的孔，其中密封层是具有几个单层厚度的聚酰亚胺，并且其中聚酰亚胺不渗透到孔中。