公开(公告)号：US20140069716A1

公开(公告)日：2014-03-13

申请号：US14005410

申请日：2012-03-13

Applicant: MTEC CORPORATION ,  IRISO ELECTRONICS CO., LTD

Inventor： Yujiro Sugaya ,  Mitsuharu Kato

IPC: H01R13/58 ,  H01R43/02

CPC classification number: H01R13/58 ,  B29C45/14655 ,  B29C45/14836 ,  B29C2045/14131 ,  G01L19/141 ,  G01L19/147 ,  H01R43/0235 ,  H05K3/202 ,  H05K2201/049 ,  H05K2201/09118 ,  H05K2201/10636 ,  H05K2203/1316 ,  Y02P70/611

Abstract: A resin molded product for reducing the external force applied to a first element from each electroconductive member due to a pressure of a resin at the time of molding, when each of the electroconductive members and the first element are insert-molded with the resin, and a method for producing the same. A second element fixing the electroconductive members to each other is connected to each of the electroconductive members so as to lie astride each of the electroconductive members. Accordingly, even though a pressure of the resin which flows into a die has been applied to each of the electroconductive members when a resin part that covers each of the electroconductive members and the first element is formed by insert molding, the distortion occurring among each of the electroconductive members is reduced by the second element.

Abstract translation: 一种树脂模制品，用于当每个导电构件和第一元件与树脂嵌入成型时，由于模制时树脂的压力，减小从每个导电构件施加到第一元件的外力;以及 其制造方法。 将导电构件彼此固定的第二元件连接到每个导电构件，以跨越每个导电构件。 因此，即使在通过嵌件成型形成覆盖各导电体和第一元素的树脂部分时，即使向每个导电构件施加流入模具的树脂的压力， 导电构件被第二元件还原。

公开(公告)号：US20140049896A1

公开(公告)日：2014-02-20

申请号：US13586981

申请日：2012-08-16

Applicant: David S. LIN

Inventor： David S. LIN

IPC: G06F1/16

CPC classification number: H01R12/712 ,  H01R12/73 ,  H05K1/141 ,  H05K3/32 ,  H05K3/3436 ,  H05K2201/042 ,  H05K2201/049 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10962 ,  H05K2203/176

Abstract: An integrated circuit assembly includes a main board unit mounted fixedly on and connected electrically to an external circuit board, a daughter board unit disposed on and connected detachably to the main board unit, and an integrated circuit device mounted fixedly on and connected electrically to the daughter board unit. When the daughter board unit is connected to the main board unit, the integrated circuit device is connected electrically to the external circuit board via the main board unit and the daughter board unit.

Abstract translation: 集成电路组件包括固定地安装在电连接到外部电路板的主板单元，以及可拆卸地设置在主板单元上并且可拆卸地连接到主板单元的子板单元，以及集成电路装置，其固定地安装在电子上并连接到该女儿 板单位。 当子板单元连接到主板单元时，集成电路器件经由主板单元和子板单元电连接到外部电路板。

公开(公告)号：US20140016242A1

公开(公告)日：2014-01-16

申请号：US14027685

申请日：2013-09-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuo HATTORI ,  Isamu FUJIMOTO

IPC: H01G4/01

CPC classification number: H01G4/12 ,  H01G2/06 ,  H01G4/01 ,  H01G4/224 ,  H01G4/30 ,  H05K1/0271 ,  H05K1/141 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/041 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10015 ,  H05K2201/2045 ,  Y02P70/611

Abstract: A multilayer ceramic capacitor includes flat-shaped inner electrodes that are laminated. An interposer includes an insulating substrate that is larger than contours of the multilayer ceramic capacitor. A first mounting electrode that mounts the multilayer ceramic capacitor is located on a first principal surface of the insulating substrate, and a first external connection electrode for connection to an external circuit board located on a second principal surface. The multilayer ceramic capacitor is mounted onto the interposer in such a way that the principal surfaces of the inner electrodes are parallel or substantially parallel to the principal surface of the interposer, that is, the first and second principal surfaces of the insulating substrate.

Abstract translation: 多层陶瓷电容器包括层叠的扁平状内部电极。 插入器包括比多层陶瓷电容器的轮廓大的绝缘基板。 安装多层陶瓷电容器的第一安装电极位于绝缘基板的第一主表面上，以及用于连接到位于第二主表面上的外部电路板的第一外部连接电极。 多层陶瓷电容器以这样的方式安装到内插器上，使得内部电极的主表面平行或基本上平行于中介层的主表面，即绝缘基板的第一和第二主表面。

公开(公告)号：US20140007425A1

公开(公告)日：2014-01-09

申请号：US13542178

申请日：2012-07-05

Applicant: Ju-Mei LU ,  Yao-Min Huang ,  Jui-Chin Peng ,  Shih-Ting Yang ,  Chao-Ching Huang

Inventor： Ju-Mei LU ,  Yao-Min Huang ,  Jui-Chin Peng ,  Shih-Ting Yang ,  Chao-Ching Huang

IPC: H05K3/22

CPC classification number: B81C1/00309 ,  B81C1/00269 ,  B81C1/00873 ,  B81C2203/0118 ,  H05K3/0052 ,  H05K3/34 ,  H05K2201/049 ,  H05K2201/10083 ,  H05K2201/10371 ,  Y10T29/49128

Abstract: A manufacturing method of electronic packaging includes the steps of preparing a metallic plate having an array of cover portions, soldering the metallic plate to a circuit board having encapsulated areas corresponding to the cover portions and employing a cutting process to obtain multiple electronic packages. Thus, the invention has the advantages of low cost and high efficiency

Abstract translation: 电子封装的制造方法包括以下步骤：制备具有盖部分阵列的金属板，将金属板焊接到具有与盖部分对应的封装区域的电路板，并采用切割工艺以获得多个电子封装。 因此，本发明具有成本低，效率高的优点

公开(公告)号：US20130329389A1

公开(公告)日：2013-12-12

申请号：US13906695

申请日：2013-05-31

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Kazuo HATTORI ,  Isamu FUJIMOTO

IPC: H05K1/02

CPC classification number: H05K1/181 ,  H01G4/232 ,  H01G4/30 ,  H01G4/35 ,  H05K1/0216 ,  H05K1/141 ,  H05K3/1258 ,  H05K3/341 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/09181 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/10636 ,  H05K2201/10962 ,  H05K2201/10984 ,  H05K2201/2045 ,  Y02P70/611 ,  Y02P70/613

Abstract: A chip-component structure includes an interposer on which a multilayer capacitor is mounted. The interposer includes component connecting electrodes, external connection electrodes, side electrodes, and in-hole electrodes. The component connecting electrodes and the external connection electrodes are electrically connected by the side electrodes and the in-hole electrodes. Outer electrodes of the capacitor are joined to the component connecting electrodes.

公开(公告)号：US08472204B2

公开(公告)日：2013-06-25

申请号：US13130680

申请日：2010-09-15

Applicant: Mark E. Leibowitz ,  Michael M. Borthwick ,  Saeed Karamooz

Inventor： Mark E. Leibowitz ,  Michael M. Borthwick ,  Saeed Karamooz

IPC: H05K1/14 ,  H05K5/00

CPC classification number: H05K7/1461 ,  G06F1/186 ,  H05K1/144 ,  H05K2201/042 ,  H05K2201/049

Abstract: A card assembly is disclosed comprising a carrier host card, an interposer printed wiring board (PWB) situated between the carrier host card and a hosted card, wherein the carrier host card and the interposer printed wiring board (PWB) are configured to have a space there-between. The card assembly further comprising a customized front panel including a first cutout for the carrier host card and a second cutout for said hosted card.

Abstract translation: 公开了一种卡组件，其包括载体主机卡，位于载体主机卡和托管卡之间的插入器印刷布线板（PWB），其中载体主机卡和插入器印刷布线板（PWB）被配置为具有空间 之间。 卡组件还包括定制的前面板，其包括用于承载主机卡的第一切口和用于所述托管卡的第二切口。

公开(公告)号：US20130077252A1

公开(公告)日：2013-03-28

申请号：US13310101

申请日：2011-12-02

Applicant: Ted Ju ,  Chin Chi Lin

Inventor： Ted Ju ,  Chin Chi Lin

IPC: H05K7/20 ,  H05K1/14

CPC classification number: H01L23/36 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/117 ,  H05K1/141 ,  H05K3/368 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10477 ,  H01L2924/00

Abstract: The invention relates to an electrical connector assembly. The electrical connector assembly includes a main circuit board having a through hole, a processor, and an auxiliary circuit board. The processor includes a chip and a substrate. The chip is electrically connected to the substrate and located in the through hole. The substrate is at least partially located in the through hole. The auxiliary circuit board has a transitional connecting surface. A first conducting region and a second conducting region electrically connected to each other are disposed on the transitional connecting surface. The first conducting region is electrically connected to the substrate, and the second conducting region is electrically connected to the main circuit board.

Abstract translation: 本发明涉及电连接器组件。 电连接器组件包括具有通孔的主电路板，处理器和辅助电路板。 处理器包括芯片和基板。 芯片电连接到基板并位于通孔中。 衬底至少部分地位于通孔中。 辅助电路板具有过渡连接面。 电连接的第一导电区域和第二导电区域设置在过渡连接面上。 第一导电区域电连接到基板，并且第二导电区域电连接到主电路板。

公开(公告)号：US20130037911A1

公开(公告)日：2013-02-14

申请号：US13569454

申请日：2012-08-08

Applicant: Kazuo HATTORI ,  Isamu FUJIMOTO

Inventor： Kazuo HATTORI ,  Isamu FUJIMOTO

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01G4/232 ,  H01G2/065 ,  H01G4/12 ,  H01L23/13 ,  H01L23/49805 ,  H01L28/40 ,  H01L2924/0002 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/099 ,  H05K2201/10015 ,  Y02P70/613 ,  H01L2924/00

Abstract: In a chip-component structure, a monolithic ceramic capacitor is a structure including a predetermined number of substantially flat internal electrodes stacked on each other. An interposer includes a substrate larger than the outer shape of the monolithic ceramic capacitor. The substrate includes a first major surface on which first front electrodes for use in mounting the monolithic ceramic capacitor are disposed and a second major surface on which first back electrodes for use in connecting to an external circuit board are disposed. The interposer includes a depression in its side surface. The depression includes a wall surface on which a connection conductor is disposed. The front surface of the substrate is overlaid with resist films extending along its edges.

Abstract translation: 在芯片部件结构中，单片陶瓷电容器是包括彼此堆叠的预定数量的基本平坦的内部电极的结构。 插入器包括比单片陶瓷电容器的外形大的衬底。 基板包括第一主表面，第一主表面设置有用于安装单片陶瓷电容器的第一前电极，并且第二主表面设置有用于连接到外部电路板的第一背电极。 插入件包括其侧表面上的凹陷。 凹陷包括壁表面，连接导体设置在该壁表面上。 衬底的前表面与沿其边缘延伸的抗蚀剂膜重叠。

公开(公告)号：US08374470B2

公开(公告)日：2013-02-12

申请号：US12559637

申请日：2009-09-15

Applicant: Takuma Ban ,  Yasunobu Matsuoka

Inventor： Takuma Ban ,  Yasunobu Matsuoka

IPC: G02B6/30 ,  G02B6/32

CPC classification number: G02B6/43 ,  H01L31/0203 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0274 ,  H05K1/141 ,  H05K1/183 ,  H05K2201/049 ,  H05K2201/09845 ,  H05K2201/10727 ,  H05K2203/167 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A structure which stably achieves electrical coupling, and is capable of efficient optical coupling is provided. Optical coupling is achieved with the lower surface of an opto-electric package and the upper surface of an opto-electric hybrid board. On the other hand, electrical connection is achieved by means of contact between electrodes on the side surfaces of the opto-electric package and electrodes on the inner-wall side surfaces of a socket mounted on the opto-electric hybrid board. The electrodes are in electrical contact with electrical wiring.

Abstract translation: 提供了稳定地实现电耦合并且能够有效地进行光耦合的结构。 通过光电封装的下表面和光电混合板的上表面实现光耦合。 另一方面，通过光电封装的侧面的电极与安装在光电混合基板上的插座的内壁侧面的电极之间的接触来实现电连接。 电极与电气线路电接触。

公开(公告)号：US20120299615A1

公开(公告)日：2012-11-29

申请号：US13192782

申请日：2011-07-28

Applicant: FA-SHENG HUANG

Inventor： FA-SHENG HUANG

IPC: G01R31/28

CPC classification number: H05K1/0268 ,  H05K1/141 ,  H05K3/4015 ,  H05K2201/049

Abstract: An assistant test circuit board for assisting a tester to test a number of signal welds and a number of ground welds on a printed circuit board includes a ground pin, a same number of ground pads as ground welds, test pads, and a same number of test pins as signal welds. Each test pad and each ground pad located on a fist side of the circuit board are soldered to the corresponding signal weld and ground weld, while the test pins and the ground pin are connected to the tester.

Abstract translation: 用于辅助测试仪测试印刷电路板上的多个信号焊缝和多个接地焊缝的辅助测试电路板包括接地引脚，与接地焊缝相同数量的接地焊盘，测试焊盘和相同数量的 测试引脚作为信号焊缝。 每个测试焊盘和位于电路板第一侧的每个接地焊盘焊接到相应的信号焊接和接地焊缝，而测试引脚和接地引脚连接到测试仪。