公开(公告)号：US5838549A

公开(公告)日：1998-11-17

申请号：US788423

申请日：1997-01-27

Applicant: Tatsuya Nagata ,  Hiroya Shimizu ,  Atsushi Nakamura ,  Hideshi Fukumoto ,  Toshio Sugano

Inventor： Tatsuya Nagata ,  Hiroya Shimizu ,  Atsushi Nakamura ,  Hideshi Fukumoto ,  Toshio Sugano

IPC: H05K3/46 ,  H01L27/10 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H01R9/09

CPC classification number: H05K1/117 ,  H01R12/721 ,  H05K1/0216 ,  H01R23/6873 ,  H05K1/0224 ,  H05K2201/0191 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09481 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K3/429 ,  Y10S439/941

Abstract: In semiconductor modules having a plurality of semiconductor devices mounted on a multilayer printed circuit boards as the processing speed increases, a short circuit current flowing through CMOS devices in the semiconductor devices during operation can cause noise because of ground inductance or power supply inductance. This noise can result in erroneous operations. To solve this problem, the power supply layer or grand layer that is connected to either the power supply terminal Vcc or the ground terminal Gnd of each semiconductor memory, which is located farther from the connection terminals, is arranged closer to the semiconductor memories with this arrangement, the short circuit current flowing through the semiconductor memories is more strongly magnetically coupled with the power supply layer or ground layer arranged close to them. Thus, it is possible to reduce the effective inductance. This, in turn, reduces noise, making it possible to provide a semiconductor module with an increased processing speed.

Abstract translation: 在处理速度增加时，具有安装在多层印刷电路板上的多个半导体器件的半导体模块中，在工作期间流过半导体器件中的CMOS器件的短路电流可能由于接地电感或电源电感而引起噪声。 这种噪音可能导致错误的操作。 为了解决这个问题，连接到距连接端子更远的每个半导体存储器的电源端子Vcc或接地端子Gnd的电源层或者大层被布置成更靠近半导体存储器 布置时，流过半导体存储器的短路电流与靠近它们布置的电源层或接地层更牢固地磁耦合。 因此，可以降低有效电感。 这反过来降低了噪声，使得可以提供具有增加的处理速度的半导体模块。

公开(公告)号：US5590030A

公开(公告)日：1996-12-31

申请号：US291893

申请日：1994-08-17

Applicant: Masatsugu Kametani ,  Kazuhiro Umekita

Inventor： Masatsugu Kametani ,  Kazuhiro Umekita

IPC: H05K1/11 ,  H01L23/467 ,  H01L23/538 ,  H05K1/02 ,  H05K3/34 ,  H05K3/42 ,  H05K3/46 ,  H05K7/20

CPC classification number: H05K1/0207 ,  H01L23/467 ,  H01L23/5383 ,  H01L23/5384 ,  H05K3/429 ,  H05K3/4641 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0201 ,  H05K1/0206 ,  H05K2201/0209 ,  H05K2201/0352 ,  H05K2201/062 ,  H05K2201/09327 ,  H05K2201/09581 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09881 ,  H05K2201/10689 ,  H05K3/3447

Abstract: A circuit board includes a circuit-conductor layer, a ground layer and a power source layer superposed in a multilayer form through dielectric layers therebetween. A heat conduction through inside of the circuit board is enhanced so that circuit chips mounted on the circuit board can be cooled down to a level capable of operating normally. The circuit board can be formed to be compact. In order to enhance the heat transfer in the circuit board, at least one of the ground layer and power source layer is formed in a multilayer manner. It is preferable to form these layers at a thickness larger than that of the circuit-conductor layer. Further, preferably, the pin of the chip mounted on the board and at least one of the ground layer and power supply layer are connected to each other in such a manner as to enhance the heat conduction.

Abstract translation: 电路板包括电路导体层，接地层和通过其间的介电层以多层形式叠加的电源层。 增加了通过电路板内部的热传导，使得安装在电路板上的电路芯片可被冷却到能够正常工作的水平。 电路板可以形成为紧凑。 为了增强电路板中的热传递，接地层和电源层中的至少一个以多层形式形成。 优选以比电路导体层的厚度大的方式形成这些层。 此外，优选地，安装在板上的芯片的引脚和接地层和电源层中的至少一个彼此连接以增强热传导。

公开(公告)号：US5418690A

公开(公告)日：1995-05-23

申请号：US309554

申请日：1994-09-20

Applicant: Robert B. Conn ,  Darleen Mayo ,  Thurston B. Youngs, Jr.

Inventor： Robert B. Conn ,  Darleen Mayo ,  Thurston B. Youngs, Jr.

IPC: H05K1/00 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0265 ,  H05K3/4641 ,  H05K1/0262 ,  H05K1/0289 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/09327 ,  H05K2201/09336

Abstract: Multiple circuit functions embodied in electrical circuit lines and areas are supported by a multilayered printed circuit board of various lengths and widths (defining "x" and "y" directions) and of various thicknesses (defining a "z" direction) all on a single board. Several ways of achieving such variations in thickness include providing two layer subassemblies arranged in an alternate and intermediate manner, one subassembly being adapted to support electrical circuit lines and areas, and the other subassembly being formed of thin film dielectric material of various precalculated thicknesses. Another way of achieving a variation in thickness is to limit the surface covered by circuit lines with a pre-calculated core thickness.

Abstract translation: 在电路线路和区域中实现的多电路功能由各种长度和宽度（定义“x”和“y”方向）和各种厚度（限定“z”方向）的多层印刷电路板支持， 板。 实现这种厚度变化的几种方式包括提供以交替和中间方式布置的两层子组件，一个子组件适于支撑电路线和区域，而另一子组件由各种预先计算厚度的薄膜电介质材料形成。 实现厚度变化的另一种方法是以预先计算的芯厚限制电路线覆盖的表面。

公开(公告)号：US4973799A

公开(公告)日：1990-11-27

申请号：US396342

申请日：1989-08-21

Applicant: Utami Soma ,  Yasufumi Koseki ,  Minoru Asakawa

Inventor： Utami Soma ,  Yasufumi Koseki ,  Minoru Asakawa

IPC: G03G21/00 ,  G03G15/00 ,  H05K1/00 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0218 ,  G03G15/50 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09327 ,  H05K2201/10553 ,  H05K2201/10689

Abstract: A circuit board for mounting a CPU for controlling an image processing apparatus, comprising a multilayered circuit board for mounting the CPU, and a shield layer for shielding the multilayered circuit board without connecting the shield layer to the circuits of the board. The circuits of the multilayered circuit board are produced by a printing or an electrolytic plating method or an electroless plating method.

Abstract translation: 一种用于安装用于控制图像处理装置的CPU的电路板，包括用于安装CPU的多层电路板和用于屏蔽多层电路板而不将屏蔽层连接到电路板的电路的屏蔽层。 多层电路板的电路通过印刷或电解电镀法或无电镀法制造。

公开(公告)号：US3519959A

公开(公告)日：1970-07-07

申请号：US3519959D

申请日：1966-03-24

Applicant: BURROUGHS CORP

Inventor： BEWLEY LAWRENCE L ,  WHITE KENNETH H ,  JORGENSEN ARNOLD J

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/46 ,  H05K1/04 ,  H05K1/14 ,  H05K3/30

CPC classification number: H05K3/4084 ,  H05K1/024 ,  H05K1/0262 ,  H05K1/0263 ,  H05K3/4092 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/044 ,  H05K2201/09327 ,  H05K2201/10303 ,  H05K2203/063 ,  Y10T29/4913

公开(公告)号：US20240015897A1

公开(公告)日：2024-01-11

申请号：US18126605

申请日：2023-03-27

Applicant: Samsung Display Co., Ltd.

Inventor： HYO-CHUL LEE ,  YOUNYEE KANG ,  JI-WON KIM ,  SEUNGIN BAEK ,  IN SOO WANG

IPC: H05K5/00 ,  H05K1/18

CPC classification number: H05K5/0018 ,  H05K1/189 ,  H05K5/0086 ,  H05K2201/10128 ,  H05K2201/09327

Abstract: A circuit board includes a first body part, a second body part and a connection part. The first body part includes a first contact surface and has a multi-layered structure. The second body part includes a second contact surface, has a multi-layered structure, and includes a first signal line spaced apart from the second contact surface. The connection part includes a third contact surface between the first contact surface and the second contact surface, and connects the first body part and the second body part to each other.

公开(公告)号：US20180206332A1

公开(公告)日：2018-07-19

申请号：US15923048

申请日：2018-03-16

Applicant: GigaLane Co., Ltd.

Inventor： Sang Pil Kim ,  Da Yeon Lee ,  Hwang Sub Koo ,  Hyun Je Kim ,  Hee Seok Jung

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0225 ,  H05K1/028 ,  H05K1/0393 ,  H05K3/0044 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09327

Abstract: Disclosed is a flexible circuit board having a three-layer dielectric body and four-layer ground layer structure. A flexible circuit board having a three-layer dielectric body and four-layer ground layer structure, according to the present invention, comprises: a first dielectric body; a second dielectric body facing the flat surface of the first dielectric body; a third dielectric body facing the bottom side of the first dielectric body; a signal line formed on the flat surface of the first dielectric body; a pair of first ground layers laminated on the flat surface of the first dielectric body and having the signal line therebetween; second ground layers laminated on the bottom side of the first dielectric body so as to correspond to the first ground layers; a third ground layer laminated on the flat surface of the second dielectric body; and a fourth ground layer laminated on the bottom side of the third dielectric body.

公开(公告)号：US20180158490A1

公开(公告)日：2018-06-07

申请号：US15823932

申请日：2017-11-28

Applicant: Axis AB

Inventor： Henrik HOVMOLLER

IPC: G11C5/02 ,  H01L27/02 ,  G11C5/04 ,  G11C5/06 ,  G11C8/06

CPC classification number: G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C8/06 ,  G11C8/12 ,  H01L27/0207 ,  H05K1/0243 ,  H05K2201/09327 ,  H05K2201/10159 ,  H05K2201/10545

Abstract: A memory arrangement and method to arrange memories are disclosed. The memory arrangement comprises at least two memory chips (M1, M2) arranged on a Printed Circuit Board, PCB. A first memory chip (M1) is arranged on a first surface of the PCB, a second memory chip (M2) is arranged on a second surface of the PCB. The second memory chip (M2) is placed back to back to the first memory chip (M1) and oriented such that respective pins having the same function on the first memory chip (M1) and the second memory chip (M2) are placed opposite to each other and connected by vias to respective signal traces arranged between the first and second surfaces of the PCB.

公开(公告)号：US09520160B2

公开(公告)日：2016-12-13

申请号：US14229483

申请日：2014-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chil-Nam Yoon ,  Seon-Ryeong Kang ,  Hui-Chong Shin

IPC: H05K1/11 ,  H05K1/14 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4093 ,  H05K1/02

CPC classification number: G11C5/06 ,  G11C7/109 ,  G11C11/4093 ,  G11C2207/105 ,  H05K1/0225 ,  H05K1/0253 ,  H05K2201/09327 ,  H05K2201/10159

Abstract: A memory module includes a plurality of semiconductor memory devices and a circuit board. The circuit board is electrically connected to the plurality of semiconductor memory devices, and a signal line is disposed in the outermost layer of the circuit board. An electrical reference for the signal line is provided in a layer of the circuit board that is not adjacent to the outermost layer. Accordingly, an impedance of the signal line may be increased, and signal integrity of a signal transmitted through the signal line may be improved.

Abstract translation: 存储器模块包括多个半导体存储器件和电路板。 电路板电连接到多个半导体存储器件，信号线设置在电路板的最外层中。 在不与最外层相邻的电路板的层中提供用于信号线的电参考。 因此，可以增加信号线的阻抗，并且可以提高通过信号线传输的信号的信号完整性。

公开(公告)号：US09401531B2

公开(公告)日：2016-07-26

申请号：US14191595

申请日：2014-02-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kanto Iida ,  Shigeru Tago

IPC: H01P3/08 ,  H03H7/38 ,  H05K1/02

CPC classification number: H01P3/08 ,  H03H7/38 ,  H05K1/0225 ,  H05K1/0253 ,  H05K2201/09327 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/09727

Abstract: A high-frequency signal transmission line includes a dielectric body including a plurality of dielectric sheets. A signal line is provided in the dielectric body. A connector is mounted on a first main surface of the dielectric body and electrically connected to the signal line. A ground conductor is provided on a second main surface side of the dielectric body, compared with the signal line, and faces the signal line across the dielectric sheet. In the ground conductor, conductor-missing portions are provided in which no conductors are provided in at least portions of regions overlapping with the signal line in planar in connection portions. Adjustment conductors are provided in the second main surface of the dielectric body, and overlap with at least portions of the conductor-missing portions in the planar view.

Abstract translation: 高频信号传输线包括包括多个电介质片的电介体。 信号线设置在电介质体中。 连接器安装在电介质体的第一主表面上并电连接到信号线。 与信号线相比，在电介质体的第二主表面侧设置接地导体，并且面对跨越电介质片的信号线。 在接地导体中，提供导体缺失部分，其中在与连接部分中平面的信号线重叠的区域的至少部分中不设置导体。 调整导体设置在电介质体的第二主表面中，并且在俯视图中与导体缺失部分的至少一部分重叠。