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    Method for making electrical interconnections between layers of an IC package
    62.
    发明授权
    Method for making electrical interconnections between layers of an IC package 失效
    用于在IC封装的层之间进行电互连的方法

    公开(公告)号：US5992012A

    公开(公告)日：1999-11-30

    申请号：US971769

    申请日：1997-11-17

    Applicant: Scott Kirkman

    Inventor： Scott Kirkman

    IPC: H01L21/48 ,  H05K1/00 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/36

    CPC classification number: H05K3/0011 ,  H01L21/486 ,  H05K1/115 ,  H05K3/4038 ,  H01L2224/16225 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0287 ,  H05K1/113 ,  H05K2201/09609 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/0235 ,  H05K2203/0759 ,  H05K2203/308 ,  H05K3/427 ,  Y10T29/49126 ,  Y10T29/49165

    Abstract: In the manufacture of Printed Circuit (PC) boards, conductors are placed in a base layer of glass cloth. The conductors penetrate the thickness of the cloth and can be arranged to form a matrix or grid. The arrangement of cloth and conductors is then cured with resin with the wire lengths disposed within the cured board core. The wire lengths can be made flush with the board core surfaces and become the electrical conductors between circuitry on such surfaces. In one embodiment, the wire is removed leaving a finished hole ready for standard through-hole plating. These finished circuit boards can be stacked and laminated forming through, blind, or buried vias. One or more finished circuit boards with imbedded vias can be used as circuitry redistribution layers to avoid dense circuit patterns in applications such as in flip-chip mounting of integrated circuit chips. In another embodiment, the conductors are imbedded in the glass cloth with sufficient density to form a composite thick conductor. Other layers can then be laminated or built up on this composite and multiple vias can then be formed to the thick conductor using conventional techniques.

    Abstract translation: 在印刷电路板（PC）的制造中，将导体放置在玻璃布的基层中。 导体穿过布的厚度，并且可以布置成形成矩阵或网格。 然后用树脂固化布和导体的布置，其中线长度设置在固化的板芯内。 电线长度可以与电路板芯表面齐平并成为这些表面上的电路之间的电导体。 在一个实施例中，去除线，留下准备好用于标准通孔电镀的成品孔。 这些完成的电路板可以堆叠并层压成型，盲孔或埋入通孔。 具有嵌入式通孔的一个或多个成品电路板可以用作电路再分配层，以避免在诸如集成电路芯片的倒装芯片安装的应用中的密集电路图案。 在另一个实施例中，导体以足够的密度嵌入玻璃布中以形成复合厚导体。 然后可以在该复合材料上层叠或构建其它层，然后可以使用常规技术将多个通孔形成为厚导体。

    Core for electrical connecting substrates and electrical connecting substrates with core, as well as process for the production thereof
    64.
    发明授权
    Core for electrical connecting substrates and electrical connecting substrates with core, as well as process for the production thereof 失效
    用于电连接基板和具有芯的电连接基板的芯，以及用于其生产的工艺

    公开(公告)号：US5442143A

    公开(公告)日：1995-08-15

    申请号：US216717

    申请日：1994-03-23

    Applicant: Walter Schmidt ,  Marco Martinelli

    Inventor： Walter Schmidt ,  Marco Martinelli

    IPC: B32B37/00 ,  B32B7/00 ,  H01L21/00 ,  H01R9/00 ,  H05K1/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/40 ,  H05K3/46

    CPC classification number: H05K3/4038 ,  H05K1/0287 ,  H05K3/06 ,  H05K3/4602 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/068 ,  H05K2203/1476 ,  H05K3/0041 ,  H05K3/4652

    Abstract: The inventive core for electrical connecting substrates, particularly for printed circuit boards and foil circuit boards, has an inner layer (I) with a columnar structure and on either side, metallic cover layers (A,A'), the columnar structure of the inner layer (I) comprising columns (9.1,9.2), which are regularly arranged, spaced from one another and from the cover layers (A,A'), being directed transversely to the service extension of the core and made from an electrically conductive material in a matrix (6) of an electrically insulating material. The cover layers (A,A') e.g. have electrical terminals (16,16', 17,17') in the form of through-plated blind holes (13,14) on selected columns (9) of the inner layer (I) and are structured in such a way that they have a regular pattern of terminals (16,16') on the facing cover layer and terminals (17,17') on the through-connections insulated from the cover layers, this grid pattern can have a size of approximately 0.5 mm.

    Abstract translation: 用于电连接基板的本发明的芯，特别是用于印刷电路板和箔电路板的芯具有具有柱状结构的内层（I），并且在任一侧上具有金属覆盖层（A，A'），内层的柱状结构 包括彼此间隔开并且与覆盖层（A，A'）间隔开的规则排列的柱（9.1,9.2）的层（I）横向于芯的使用延伸部并且由导电材料制成 在电绝缘材料的矩阵（6）中。 覆盖层（A，A'）例如 具有在内层（I）的选定列（9）上的通电镀盲孔（13,14）形式的电端子（16,16'，17,17'），并且以这样的方式构造： 在面层的覆盖层上具有规则的端子（16,16'）图案和与覆盖层绝缘的通孔上的端子（17,17'），该网格图案可以具有大约0.5mm的尺寸。

    Ceramic wiring board and its production
    66.
    发明授权
    Ceramic wiring board and its production 失效
    陶瓷接线板及其生产

    公开(公告)号：US4792646A

    公开(公告)日：1988-12-20

    申请号：US97452

    申请日：1987-09-16

    Applicant: Eyo Enomoto

    Inventor： Eyo Enomoto

    IPC: H05K3/46 ,  H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42

    CPC classification number: H05K1/0306 ,  H05K1/0287 ,  H05K3/0055 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2203/1394 ,  H05K3/181 ,  H05K3/386 ,  H05K3/426 ,  H05K3/429 ,  Y10T29/49163 ,  Y10T29/49165

    Abstract: A ceramic substrate having a plurality of holes arranged regularly with a specified pitch can be used for an universal high density ceramic wiring board, wherein predetermined one or more holes among said plurality of holes are used as through holes for interconnecting both side circuits, and the remaining holes not used for a circuit are filled with an electrical insulating material.Said ceramic substrate of universal type can easily be produced inexpensively and within a short lead time, because said substrate requires no individual mold for each of various circuits to punch a green sheet and can be kept in stock as a fired ceramic substrate.

    Abstract translation: 具有以规定间距规则排列的多个孔的陶瓷基板可以用于通用高密度陶瓷布线板，其中所述多个孔中的预定的一个或多个孔用作用于互连两侧电路的通孔，并且 不用于电路的剩余孔填充有电绝缘材料。 所述通用型陶瓷基板可以容易地廉价地生产并且在短的提前期内，因为所述基板不需要各种电路的单独模具来冲压生片，并且可以作为烧制的陶瓷基板保存。

    High density multi-layer circuit arrangement
    68.
    发明授权
    High density multi-layer circuit arrangement 失效
    高密度多层电路布置

    公开(公告)号：US4598166A

    公开(公告)日：1986-07-01

    申请号：US638176

    申请日：1984-08-06

    Applicant: Wayne E. Neese

    Inventor： Wayne E. Neese

    IPC: H05K1/00 ,  H05K1/11 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K1/14

    CPC classification number: H05K1/116 ,  H05K1/0289 ,  H05K1/0287 ,  H05K2201/09381 ,  H05K2201/09536 ,  H05K2201/09609 ,  H05K3/4046 ,  H05K3/429 ,  H05K3/4614

    Abstract: An arrangement for constructing multi-layered printed circuits characterized by a first layer having top and bottom surfaces with the top surface including a plurality of parallel conductors divided into at least two conductor groups by a transversely oriented break across each conductor. The bottom surface further includes a plurality of parallel conductors arranged perpendicular to the conductors on the top surface and is also divided into at least two conductor groups by a transversely oriented break across each conductor. A plurality of holes extend through the first layer with, each hole adjacent to an intersecting conductor pair. A second layer including top and bottom surfaces and a plurality of plated-through holes has conductor pennants extending from selected holes in a first direction on the top surface and a second opposite direction on the bottom surface. A plurality of first and second layers are sandwiched together, with each hole of each layer in registration with the other and each conductor pennant contacting a respective first layer conductor. Conductor segments printed on the second layer top and bottom surfaces interconnect selected conductors between respective conductor groups. Additionally, two or more second layers are interconnected by via pins extending through the arrangement.

    Abstract translation: 一种用于构造多层印刷电路的装置，其特征在于具有顶表面和底表面的第一层，顶表面包括通过每个导体横向定向断裂而分成至少两个导体组的多个平行导体。 底表面还包括垂直于顶表面上的导体设置的多个平行导体，并且还通过穿过每个导体的横向取向的断路将其分成至少两个导体组。 多个孔穿过第一层，每个孔与交叉导体对相邻。 包括顶表面和底表面的第二层和多个电镀通孔具有从顶表面上的第一方向上的选定孔延伸的导体三角旗和在底表面上的第二相反方向。 多个第一层和第二层夹在一起，每层的每个孔与另一层对准，每个导体三角旗与相应的第一层导体接触。 印刷在第二层顶部和底部表面上的导体段在相应的导体组之间互连选定的导体。 此外，两个或更多个第二层通过延伸穿过该布置的通孔引脚相互连接。

    Printed board
    70.
    发明授权
    Printed board 失效
    印刷板

    公开(公告)号：US4298770A

    公开(公告)日：1981-11-03

    申请号：US69346

    申请日：1979-08-24

    Applicant: Mikio Nishihara ,  Masahiro Oda ,  Takamitsu Tsuchimoto

    Inventor： Mikio Nishihara ,  Masahiro Oda ,  Takamitsu Tsuchimoto

    IPC: H05K1/02 ,  H05K1/00 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

    CPC classification number: H05K1/116 ,  H05K1/0289 ,  H05K2201/09381 ,  H05K2201/09609 ,  H05K3/429

    Abstract: A printed board comprising a plurality of through holes formed therein and located on intersecting points of an X-Y orthogonal basic grid, and an oblique conductor pattern, wherein conductors are formed along channels arranged in accordance with a principle that one conductor passes between adjacent grid points arranged in the X direction, while two or more conductors pass between adjacent grid points arranged in the Y direction, and each conductor obliquely extends in a zigzag line without contacting the grid points. Such conductor pattern ensures a high density and minimum length of wiring.

    Abstract translation: 一种印刷电路板，包括形成在其中并位于XY正交基本栅极的交叉点上的多个通孔和倾斜导体图案，其中导体沿着沿着布置的通道形成，该导体根据一个导体在相邻的格栅点之间通过的原理布置 在X方向上，当两个或多个导体在沿Y方向布置的相邻栅格点之间通过时，并且每个导体以Z字形线倾斜地延伸而不接触网格点。 这种导体图形确保了高密度和最小布线长度。

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