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    Semiconductor Assembly
    71.
    发明申请
    Semiconductor Assembly 有权

    公开(公告)号：US20220199528A1

    公开(公告)日：2022-06-23

    申请号：US17128597

    申请日：2020-12-21

    Applicant: NVIDIA Corp.

    Inventor： Jacky Qiu ,  Martin Ding ,  Jerry Zhou ,  Minto Zheng

    IPC: H01L23/528 ,  H01L23/14 ,  H01L23/367 ,  H01L23/522 ,  H05K7/20 ,  H05K1/11 ,  H05K1/02

    Abstract: A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.

    EFFICIENT SOFTMAX COMPUTATION
    74.
    发明申请
    EFFICIENT SOFTMAX COMPUTATION 有权

    公开(公告)号：US20220067513A1

    公开(公告)日：2022-03-03

    申请号：US17112795

    申请日：2020-12-04

    Applicant: NVIDIA Corp.

    Inventor： Jacob Robert Stevens ,  Rangharajan Venkatesan ,  Steve Haihang Dai ,  Brucek Khailany

    IPC: G06N3/08 ,  G06N3/063 ,  G06F7/552 ,  G06F7/50

    Abstract: Solutions improving efficiency of Softmax computation applied for efficient deep learning inference in transformers and other neural networks. The solutions utilize a reduced-precision implementation of various operations in Softmax, replacing ex with 2x to reduce instruction overhead associated with computing ex, and replacing floating point max computation with integer max computation. Further described is a scalable implementation that decomposes Softmax into UnNormalized Softmax and Normalization operations.

    Foveated display for augmented reality
    76.
    发明授权
    Foveated display for augmented reality 有权

    公开(公告)号：US11067806B2

    公开(公告)日：2021-07-20

    申请号：US16428713

    申请日：2019-05-31

    Applicant: NVIDIA Corp.

    Inventor： Jonghyun Kim ,  Youngmo Jeong ,  Michael Stengel ,  Morgan McGuire ,  David Luebke

    IPC: G02B27/01 ,  G03H1/22

    Abstract: An augmented reality display system includes a first beam path for a foveal inset image on a holographic optical element, a second beam path for a peripheral display image on the holographic optical element, and pupil position tracking logic that generates control signals to set a position of the foveal inset as perceived through the holographic optical element, to determine the peripheral display image, and to control a moveable stage.

    Package level power gating
    79.
    发明授权
    Package level power gating 有权

    公开(公告)号：US10957651B2

    公开(公告)日：2021-03-23

    申请号：US16534017

    申请日：2019-08-07

    Applicant: NVIDIA Corp.

    Inventor： Don Templeton ,  Luke Young Chang ,  Narayan Kulshrestha

    IPC: H01L23/538 ,  H01L23/50 ,  H01L25/065

    Abstract: A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.

    PACKAGE LEVEL POWER GATING
    80.
    发明申请
    PACKAGE LEVEL POWER GATING 有权

    公开(公告)号：US20210043574A1

    公开(公告)日：2021-02-11

    申请号：US16534017

    申请日：2019-08-07

    Applicant: NVIDIA Corp.

    Inventor： Don Templeton ,  Luke Young Chang ,  Narayan Kulshrestha

    IPC: H01L23/538 ,  H01L23/50 ,  H01L25/065

    Abstract: A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.

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