公开(公告)号：US20180317318A1

公开(公告)日：2018-11-01

申请号：US15950479

申请日：2018-04-11

Applicant: Seiko Epson Corporation

Inventor： Yohei YAMADA ,  Tomoyuki KAMAKURA

IPC: H05K1/02 ,  H05K1/18 ,  G01B7/16

CPC classification number: H05K1/0283 ,  G01B7/20 ,  H05K1/111 ,  H05K1/181 ,  H05K1/189 ,  H05K3/284 ,  H05K2201/0133 ,  H05K2201/0191 ,  H05K2201/09281 ,  H05K2201/09736 ,  H05K2201/10151 ,  H05K2201/10439 ,  H05K2201/2009 ,  H05K2203/1316 ,  H05K2203/1322

Abstract: A stretchable circuit board includes a stretchable substrate, a stretchable conducting film placed on one surface of the stretchable substrate and elongated in a first direction, an electric element placed on the one surface of the stretchable substrate, and a covering portion that covers a part of the stretchable conducting film and at least a part of the electric element, wherein, when an area of a first section as a section along an outer circumference of the covering portion in the stretchable conducting film is referred to as a first area and an area of a second section as a section of the stretchable conducting film orthogonal to the first direction in a location apart from the outer circumference of the covering portion toward outside is referred to as a second area, the first area is larger than the second area.

公开(公告)号：US20180263114A1

公开(公告)日：2018-09-13

申请号：US15534394

申请日：2015-12-08

Applicant: FUJIKURA LTD.

Inventor： Shingo Ogura ,  Tetsu Hammura

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0283 ,  H05K1/0271 ,  H05K1/0281 ,  H05K1/0296 ,  H05K1/118 ,  H05K1/181 ,  H05K1/189 ,  H05K3/3442 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/09409 ,  H05K2201/09845 ,  H05K2201/0989 ,  H05K2201/10522 ,  Y02P70/611

Abstract: A stretchable board includes: a base material having stretchability; first and second electronic components mounted on the base material; a wire arranged on the base material; and first and second connectors for connecting the first and second electronic components and the wire to each other. At least a portion of the first electronic component and at least a portion of the second electronic component face each other in a planned stretching direction in which the base material includes: a facing zone interposed between the first and second electronic components in a planned stretching direction and a non-facing zone other than the facing zone on the base material, in which at least a portion of the first connector or at least a portion of the second connector are arranged in the non-facing zone, and in which at least one of the wires is arranged in the non-facing zone.

公开(公告)号：US20180054177A1

公开(公告)日：2018-02-22

申请号：US15240987

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil MUDAKATTE ,  David Francis BERDY ,  Changhan Hobie YUN ,  Chengjie ZUO ,  Shiqun GU ,  Mario Francisco VELEZ ,  Jonghae KIM

IPC: H03H7/01 ,  H03H1/00 ,  H03H7/46 ,  H01L49/02

CPC classification number: H03H7/0115 ,  H01L28/10 ,  H01L28/40 ,  H03H1/0007 ,  H03H7/0138 ,  H03H7/46 ,  H03H2001/0078 ,  H03H2001/0085 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09281

Abstract: A passive device may include an inductor having interconnected trace segments. The passive device may also include parallel plate capacitors. Each of the plurality of parallel plate capacitors may have a dielectric layer between a pair of conductive plates. The parallel plate capacitors may not overlap more than one of the interconnected trace segments.

公开(公告)号：US09560762B2

公开(公告)日：2017-01-31

申请号：US14050258

申请日：2013-10-09

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi Oikawa

IPC: H01L23/64 ,  H05K1/18 ,  H05K1/02 ,  H01L23/498 ,  H01L23/66 ,  H05K3/42 ,  H05K3/46 ,  H01L21/48

CPC classification number: H05K1/18 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2224/49171 ,  H01L2924/00 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/30111 ,  H05K1/0219 ,  H05K1/0225 ,  H05K1/0236 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/0251 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09281 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed.

Abstract translation: 半导体器件包括半导体芯片，多个外部端子和基板。 电路板包括：第一主表面，其中形成电连接到半导体芯片的多个第一电极;第二主表面，其中形成有多个与多个外部端子电连接的第二电极;以及多个互连 层，设置在第一主表面和第二主表面之间，用于形成电连接第一电极和与其对应的第二电极的多个信号路径。 互连层包括多个金属构件，其分散配置在比构成信号路径的信号的信号频带的电磁波长短的距离处，在其附近形成用于形成的互连的结构部分 信号路径被改变。

公开(公告)号：US09554465B1

公开(公告)日：2017-01-24

申请号：US14593849

申请日：2015-01-09

Applicant: Flextronics AP, LLC

Inventor： Weifeng Liu ,  Anwar Mohammed ,  Dick Pang ,  Murad Kurwa

IPC: H05K1/09 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/092 ,  H05K1/0283 ,  H05K1/03 ,  H05K1/0393 ,  H05K1/147 ,  H05K1/183 ,  H05K3/285 ,  H05K2201/0133 ,  H05K2201/0162 ,  H05K2201/09218 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/09281

Abstract: A stretchable interconnect includes a plurality of electrically conductive traces formed as a complex pattern on an elastic substrate. The form of the electrically conductive traces is such that when the elastic substrate is in a relaxed, or non-stretched, state each of the electrically conductive traces forms a tortuous path, such as a waveform, along the elastic substrate. The tortuous path of the electrically conductive traces provides slack such that as the elastic substrate is stretched the slack is taken up. Once released, the elastic substrate moves from the stretched position to the relaxed, non-stretched position, and slack is reintroduced into the electrically conductive traces in the form of the original tortuous path.

Abstract translation: 可拉伸互连件包括在弹性基底上形成为复合图案的多个导电迹线。 导电迹线的形式使得当弹性基底处于松弛或非拉伸状态时，每个导电迹线沿着弹性基底形成诸如波形的曲折路径。 导电迹线的弯曲路径提供松弛，使得当弹性基底被拉伸时松弛松弛。 一旦释放，弹性基板从拉伸位置移动到松弛的非拉伸位置，并且以原始曲折路径的形式将松弛重新引入导电迹线。

公开(公告)号：US09490513B2

公开(公告)日：2016-11-08

申请号：US14503612

申请日：2014-10-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi Sasaki ,  Nobuo Ikemoto ,  Shigeru Tago

IPC: H01P3/08 ,  H01P3/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/14

CPC classification number: H01P3/003 ,  H01P3/08 ,  H01P3/085 ,  H05K1/0225 ,  H05K1/0253 ,  H05K1/0284 ,  H05K1/0393 ,  H05K1/147 ,  H05K2201/09245 ,  H05K2201/09281 ,  H05K2201/09727

Abstract: A dielectric element assembly includes a plurality of dielectric layers stacked on each other in a direction of lamination and extends in an x-axis direction. A signal line is provided in the dielectric element assembly and extends in the x-axis direction. A reference ground conductor is provided on a positive side in a z-axis direction relative to the signal line. An auxiliary ground conductor is provided on a negative side in the z-axis direction relative to the signal line. Via-hole conductors connect the reference ground conductor and the auxiliary ground conductor and are provided in the dielectric element assembly on the negative side relative to the center in a y-axis direction. A portion of the signal line in a section which includes the via-hole conductors is positioned on the positive side in the y-axis direction relative to another portion of the signal line in a section which does not include the via-hole conductors.

Abstract translation: 电介质元件组件包括在层叠方向上彼此堆叠并沿x轴方向延伸的多个电介质层。 信号线设置在电介质元件组件中并沿x轴方向延伸。 参考接地导体相对于信号线在z轴方向的正侧设置。 辅助接地导体相对于信号线设置在z轴方向的负侧。 通孔导体连接参考接地导体和辅助接地导体，并且在y轴方向相对于中心的负侧设置介质元件组件。 包括通孔导体的部分中的信号线的一部分在不包括通孔导体的部分中位于相对于信号线的另一部分的y轴方向的正侧。

公开(公告)号：US09406703B2

公开(公告)日：2016-08-02

申请号：US14532590

申请日：2014-11-04

Applicant: LG Display Co., Ltd.

Inventor： SeYeoul Kwon ,  Sangcheon Youn ,  Anna Ha

IPC: H01L27/12 ,  H05K1/02 ,  H05K1/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1244 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/78696 ,  H05K1/028 ,  H05K1/0283 ,  H05K1/16 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/051 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10128 ,  H05K2201/10166

Abstract: Provided is a configuration for a semiconductor layer and a line for reducing the segment length of the semiconductor layer with respect to the bending direction of the flexible substrate. Such a configuration reduces the probability of cracks occurring in the semiconductor layer of the thin-film transistor, thereby improving the stability and durability of the thin-film transistor employed in a curved or a flexible display device. The configuration includes a thin-film transistor (TF) on the flexible substrate. The TFT includes the semiconductor layer extending obliquely with respect to the direction of the line.

Abstract translation: 提供了一种用于半导体层和用于减小半导体层相对于柔性基板的弯曲方向的段长度的配置。 这样的结构降低了在薄膜晶体管的半导体层中发生裂纹的可能性，从而提高了在弯曲或柔性显示装置中使用的薄膜晶体管的稳定性和耐久性。 该配置包括柔性基板上的薄膜晶体管（TF）。 TFT包括相对于线的方向倾斜延伸的半导体层。

公开(公告)号：US09402306B2

公开(公告)日：2016-07-26

申请号：US13574630

申请日：2011-01-31

Applicant: Jeroen Van Den Brand ,  Gerardus Titus Van Heck ,  Margaretha Maria De Kok

Inventor： Jeroen Van Den Brand ,  Gerardus Titus Van Heck ,  Margaretha Maria De Kok

IPC: H05K1/00 ,  H05K1/02 ,  H01L27/32 ,  H01L51/52 ,  H01R4/70 ,  H05K3/36 ,  H05B33/08 ,  H05B33/10 ,  H05K13/04 ,  H01L31/0392 ,  H01L31/042 ,  G09F9/00 ,  G09F19/22 ,  H01R4/04 ,  H01R12/70 ,  H05K1/03 ,  H05K1/14 ,  H05K1/18 ,  H05K3/32

CPC classification number: H05K1/0277 ,  G09F9/00 ,  G09F19/22 ,  H01L27/3293 ,  H01L31/0392 ,  H01L31/042 ,  H01L51/5203 ,  H01L2251/5338 ,  H01L2251/5361 ,  H01R4/04 ,  H01R4/70 ,  H01R12/7076 ,  H05B33/0896 ,  H05B33/10 ,  H05K1/0283 ,  H05K1/038 ,  H05K1/147 ,  H05K1/189 ,  H05K3/321 ,  H05K3/325 ,  H05K3/365 ,  H05K13/04 ,  H05K2201/029 ,  H05K2201/0311 ,  H05K2201/046 ,  H05K2201/083 ,  H05K2201/09081 ,  H05K2201/09281 ,  H05K2201/10106 ,  H05K2201/10287 ,  H05K2201/10484 ,  Y02E10/50 ,  Y10T29/4913

Abstract: An assembly of a plurality of tiles (1) with a carrier (40). The tiles (1) comprise a foil (20) with an electro-physical transducer (10) and electrical connectors (24, 28) to said transducer. The tiles are mechanically and electrically coupled to the carrier in a connection portion (1c) of said tiles.

Abstract translation: 具有载体（40）的多个瓦片（1）的组件。 瓦片（1）包括具有电物理换能器（10）的箔（20）和到所述换能器的电连接器（24,28）。 所述瓦片在所述瓦片的连接部分（1c）中机械地和电耦合到所述载体。

公开(公告)号：US20150234497A1

公开(公告)日：2015-08-20

申请号：US14622357

申请日：2015-02-13

Applicant: MStar Semiconductor, Inc.

Inventor： Guo-Kiang Hung ,  Chien-Chuan Chen ,  Chao-Yang Kuo

IPC: G06F3/044 ,  G06F3/045

CPC classification number: G06F3/044 ,  H05K1/11 ,  H05K1/167 ,  H05K2201/09263 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/097 ,  H05K2201/10053

Abstract: An electrode of a self-capacitive touch panel is provided. The electrode, coupled to a control circuit of the self-capacitive touch panel via a conducting wire, includes: a serpentine portion, having a first side; a main portion, having a second side; and a connecting portion, connected to the first side and the second side to connect the serpentine portion and the main portion. A length of the connecting portion is smaller than a length of the first side and a length of the second side.

Abstract translation: 提供了一种自电容式触摸面板的电极。 经由导线与电容式触摸屏的控制电路相连的电极包括：具有第一侧的蛇形部分; 主要部分，具有第二面; 以及连接部分，连接到第一侧和第二侧以连接蛇形部分和主要部分。 连接部分的长度小于第一侧的长度和第二侧的长度。

公开(公告)号：US20150060393A1

公开(公告)日：2015-03-05

申请号：US14012173

申请日：2013-08-28

Applicant: RONALD STEVEN COK

Inventor： RONALD STEVEN COK

IPC: H05K3/12

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate, a first stamp, and a different multi-level second stamp. A curable bottom layer is provided over the substrate. One or more bottom-layer micro-channels) are imprinted in the curable bottom layer with the first stamp and a bottom-layer micro-wire formed in each bottom-layer micro-channel. A curable multi-layer is formed adjacent to and in contact with the cured bottom layer. First and second multi-layer micro-channels and a top-layer micro-channel are imprinted in the curable multi-layer with the multi-level second stamp. Either two bottom-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a top-layer micro-wire or two top-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a bottom-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供衬底，第一印模和不同的多级第二印模。 在基板上设置可固化的底层。 一个或多个底层微通道）印刷在可固化底层中，第一印模和底层微线形成在每个底层微通道中。 在固化的底层附近形成可固化的多层，并且与固化的底层接触。 第一和第二多层微通道和顶层微通道用多级第二印记印在可固化多层中。 两个底层微电线通过第一和第二多层微线电连接，并且顶层微线或两个顶层微线通过第一和第二多层微电子电连接 电线和底层微线。