公开(公告)号：US20060226533A1

公开(公告)日：2006-10-12

申请号：US11103048

申请日：2005-04-11

Applicant: Shin-Shing Jiang ,  Sheng-Yuan Lee

Inventor： Shin-Shing Jiang ,  Sheng-Yuan Lee

IPC: H01L23/04

CPC classification number: H01L23/66 ,  H01L23/49827 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09627 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/0979 ,  H01L2924/00

Abstract: The invention discloses a via connection structure with compensative area on a reference plane. The substrate has several conductive layers isolated by the insulation layers. When two conductive lines formed on different conductive layers where a reference plane is sandwiched in, these two conductive lines are not electrical connected because of the insulation layers. Furthermore, a via connection structure is common used to connect these two conductive lines. When a non-conductive area, i.e. the compensative area, on the reference plane is overlapped with a portion of one conductive line and is close to the via connection structure, it compensates the capacitive effect of the via connection structure. By this compensative area and the variety of the via connection structure, the vertical connection between different layers has a well impedance-matched condition and transmits the signal correctly

Abstract translation: 本发明公开了一种在参考平面上具有补偿区域的通孔连接结构。 衬底具有由绝缘层隔离的多个导电层。 当形成在不同导电层上的两个导线被夹在基准面上时，这两条导线由于绝缘层而不是电连接的。 此外，通常使用通孔连接结构来连接这两条导线。 当参考平面上的非导电区域（即，补偿区域）与一条导线的一部分重叠并且靠近通孔连接结构时，它补偿了通孔连接结构的电容效应。 通过该补偿区域和通孔连接结构的种类，不同层之间的垂直连接具有良好的阻抗匹配条件并正确传输信号

公开(公告)号：US07105911B2

公开(公告)日：2006-09-12

申请号：US10684812

申请日：2003-10-15

Applicant: Koki Ishizaki ,  Takeshi Shirato

Inventor： Koki Ishizaki ,  Takeshi Shirato

IPC: H01L29/00

CPC classification number: H01C17/242 ,  H05K1/092 ,  H05K1/167 ,  H05K3/4644 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/107 ,  H05K2203/171

Abstract: A multilayer electronic substrate is manufactured by employed: a first conductor layer arranged on an insulating substrate; an insulator arranged on the first conductor layer; a resistor arranged on the insulator; and second conductor layers for sandwiching the resistor to be connected to this resistor. In this multilayer electronic substrate, the resistor is trimmed so as to adjust an electric characteristic of a circuit, and a portion of the first conductor layer, which corresponds to a trimming portion of the resistor, is constituted by a first insulating region.

Abstract translation: 通过采用多层电子基板制造：第一导体层，布置在绝缘基板上; 布置在所述第一导体层上的绝缘体; 布置在绝缘体上的电阻器; 以及用于夹持要连接到该电阻器的电阻器的第二导体层。 在该多层电子基板中，对电阻进行修整以调整电路的电特性，并且与电阻器的修整部对应的第一导体层的一部分由第一绝缘区域构成。

公开(公告)号：US20060133055A1

公开(公告)日：2006-06-22

申请号：US11304625

申请日：2005-12-16

Applicant: Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba

Inventor： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba

IPC: H05K7/08

CPC classification number: H05K1/023 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48195 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/025 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10545 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.

Abstract translation: 在存储器模块中，多个存储器安装在模块基板上，每个存储器附近的Vref和Vss之间的阻抗通过去耦电容器和Vref平面耦合到Vss，以在宽的频率范围内实现低阻抗配置，Vref平面 分别提供给各个存储器，并且Vref平面通过使用高阻抗线或高阻抗芯片部分彼此连接。 因此，可以提供一种能够有效降低自身噪声和传播噪声的用于模块的布线技术。

公开(公告)号：US07061094B2

公开(公告)日：2006-06-13

申请号：US11035953

申请日：2005-01-18

Applicant: Eiji Takahashi ,  Takeshi Nakayama

Inventor： Eiji Takahashi ,  Takeshi Nakayama

IPC: H01L23/52 ,  H01L23/12 ,  H05K3/46 ,  H01P5/02

CPC classification number: H05K1/0224 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0237 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/0969 ,  H01L2924/00

Abstract: A multilayer printed circuit board (PCB) includes a substrate; a ground layer having edges which define a gap portion, the ground layer being provided on a bottom face of the substrate; and at least two signal traces and provided on a top face of the substrate so as to straddle the gap portion and so as to be substantially parallel to each other. The multilayer PCB also includes at least one ground trace provided between the at least two signal traces and on the top face of the substrate so as to straddle the gap portion.

Abstract translation: 多层印刷电路板（PCB）包括基板; 具有限定间隙部分的边缘的接地层，所述接地层设置在所述基板的底面上; 和至少两条信号迹线，并且设置在基板的顶面上，以跨越间隙部分并且基本上彼此平行。 所述多层PCB还包括至少一个设置在所述至少两个信号迹线之间并且在所述基板的顶面上的接地迹线，以跨越所述间隙部分。

公开(公告)号：US20060065434A1

公开(公告)日：2006-03-30

申请号：US11148893

申请日：2005-06-08

Applicant: Chi-Hsing Hsu ,  Hsing-Chou Hsu

Inventor： Chi-Hsing Hsu ,  Hsing-Chou Hsu

IPC: H05K1/11

CPC classification number: H05K1/0216 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/093 ,  H05K2201/0959 ,  H05K2201/09718

Abstract: A signal transmission structure suitable for a multi-layer circuit substrate comprising a core layer and at least a dielectric layer is provided. The signal transmission structure according to the present invention comprises a first via landing pad and a reference plane. The first via landing pad is disposed on a first surface of the core layer, and covering one end of the through hole of the core layer. The dielectric layer covers the first via landing pad and the first surface of the core layer. And the first reference plane is disposed above the dielectric layer, having a first opening disposed above one end of the through hole. Wherein, the area where the first reference plane is projected on the first surface of the core layer does not overlap with the area where the first via landing pad is projected on the first surface of the core layer.

Abstract translation: 提供适用于包括芯层和至少介电层的多层电路基板的信号传输结构。 根据本发明的信号传输结构包括第一通孔着陆垫和参考平面。 第一通孔着陆垫设置在芯层的第一表面上，并且覆盖芯层的通孔的一端。 电介质层覆盖第一通孔着陆焊盘和芯层的第一表面。 并且第一参考平面设置在电介质层上方，具有设置在通孔一端的第一开口。 其中，第一参考平面投影在芯层的第一表面上的区域不与第一通孔着陆垫投射在芯层的第一表面上的区域重叠。

公开(公告)号：US20060065433A1

公开(公告)日：2006-03-30

申请号：US10953923

申请日：2004-09-29

Applicant: Charles Danoski ,  Irving Memis ,  Steven Rosser

Inventor： Charles Danoski ,  Irving Memis ,  Steven Rosser

IPC: H05K7/06

CPC classification number: H01L23/66 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/093 ,  H05K2201/09627 ,  H05K2201/09663 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

Abstract: A circuitized substrate designed to substantially eliminate impedance disruptions during passage of signals through signal lines of the substrate's circuitry. The substrate includes a first conductive layer with a plurality of conductors on which an electrical component may be positioned and electrically coupled. The pads are coupled to signal lines (e.g., using thru-holes) further within the substrate and these signal lines are further coupled to a second plurality of conductive pads located even further within the substrate. The signal lines are positioned so as to lie between the substrate's first conductive layer and a voltage plane within a third conductive layer below the second conductive layer including the signal lines. A second voltage plane may be used adjacent the first voltage plane of the third conductive layer. Thru-holes may also be used to couple the signal lines coupled to the first conductors to a second plurality of conductors which form part of the third conductive layer. A method of making the substrate, and an electrical assembly and information handling system (e.g., computer) utilizing the substrate are also disclosed.

Abstract translation: 电路化基板被设计为基本上消除信号通过基板电路的信号线时的阻抗中断。 衬底包括具有多个导体的第一导电层，电组件可以在其上定位和电耦合。 这些焊盘在衬底内进一步耦合到信号线（例如，使用通孔），并且这些信号线还被进一步耦合到位于衬底内的另外多个导电衬垫。 信号线被定位成位于衬底的第一导电层和位于包括信号线的第二导电层下面的第三导电层内的电压平面之间。 可以在第三导电层的第一电压平面附近使用第二电压平面。 通孔也可用于将耦合到第一导体的信号线耦合到形成第三导电层的一部分的第二多个导体。 还公开了制造衬底的方法，以及利用衬底的电组件和信息处理系统（例如，计算机）。

公开(公告)号：US20060057889A1

公开(公告)日：2006-03-16

申请号：US11023489

申请日：2004-12-29

Applicant: Akiyoshi Saitou

Inventor： Akiyoshi Saitou

IPC: H01R13/66

CPC classification number: H05K1/0233 ,  H05K1/0215 ,  H05K1/0224 ,  H05K1/18 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10189 ,  H05K2201/10409

Abstract: A printed circuit board has separate first, second and third sections arranged in a predetermined direction. A connector is mounted at the first section. A noise cut filter is mounted at the second section and connected to the connector. An electronic circuit component is mounted at the third section and connected to the noise cut filter. An electrically conductive power source layer is formed within the printed circuit board at a position outside a peripheral section adjacent the second section. The noise cut filter is allowed to operate without receiving any influence of noise from the power source layer. Noise is sufficiently removed at the noise cut filter. Noise is suppressed to the utmost in electric signals in the connector. Radiation of noise is reliably reduced at the connector. Electromagnetic interference can be suppressed.

Abstract translation: 印刷电路板具有沿预定方向布置的单独的第一，第二和第三部分。 连接器安装在第一部分。 噪声截止滤波器安装在第二部分并连接到连接器。 电子电路部件安装在第三部分并连接到噪声截止滤波器。 在印刷电路板的与第二部分相邻的周边部分外的位置处形成导电电源层。 允许噪声抑制滤波器工作，而不会受到来自电源层的噪声的任何影响。 噪声在噪音截止滤波器上被充分去除。 连接器中的电信号最大限度地抑制噪声。 连接器可靠地降低噪声辐射。 可以抑制电磁干扰。

公开(公告)号：US20060043572A1

公开(公告)日：2006-03-02

申请号：US10927134

申请日：2004-08-27

Applicant: Yasuhiro Sugimoto ,  Kazunaga Higo ,  Kazuhiro Suzuki

Inventor： Yasuhiro Sugimoto ,  Kazunaga Higo ,  Kazuhiro Suzuki

IPC: H01L29/40

CPC classification number: H01L23/66 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09809

Abstract: A wiring board comprising: a plate core having a first main surface and a second main surface; conductor layers including a conductor line; dielectric layers laminated alternately with said conductor layers on at least one of said first and second main surfaces; via conductors as defined herein; a signal through-hole as defined herein; a signal through-hole conductor as defined herein; a first path end pad as defined herein; a second path end pad as defined herein; a shield through-hole as defined herein; and a shield through-hole conductor as defined herein; wherein: a signal transmission path is formed as defined herein; at least one of said conductor layers is disposed on each of said first and second main surface sides; said surface conductor on said first main surface side and said conductor line form a strip line, a microstrip line, or a coplanar waveguide with constant characteristic impedance Z0; an inner surface of said shield through-hole is covered with said shield through-hole conductor; and an interaxis distance between said signal through-hole conductor and said shield through-hole conductor is adjusted as defined herein.

Abstract translation: 一种布线板，包括：板芯，具有第一主表面和第二主表面; 包括导体线的导体层; 电介质层与所述导体层交替地层叠在所述第一和第二主表面中的至少一个上; 通孔导体; 如本文所定义的信号通孔; 如本文所定义的信号通孔导体; 如本文所定义的第一路径端垫; 如本文所定义的第二路径端垫; 如本文所定义的屏蔽通孔; 和如本文所定义的屏蔽通孔导体; 其中：如本文所定义的形成信号传输路径; 所述导体层中的至少一个设置在所述第一和第二主表面侧的每一个上; 所述第一主表面侧的所述表面导体和所述导体线形成具有恒定特性阻抗Z0的带状线，微带线或共面波导; 所述屏蔽通孔的内表面被所述屏蔽通孔导体覆盖; 并且如本文所定义的那样调节所述信号通孔导体和所述屏蔽通孔导体之间的间隔距离。

公开(公告)号：US07005736B2

公开(公告)日：2006-02-28

申请号：US10335368

申请日：2002-12-30

Applicant: Edward P. Osburn

Inventor： Edward P. Osburn

IPC: H01L23/48

CPC classification number: H05K1/0262 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/1003 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method and an apparatus for improving the delivery and filtering of power to a semiconductor device is disclosed by organizing out interconnects (pins, balls, pads or other interconnects) used to carry power in a striped configuration that shortens the conductive path required between a power source and a semiconductor device and that reduces the resistance of that conductive path.

Abstract translation: 公开了一种用于改进对半导体器件的功率的传递和滤波的方法和装置，其通过组织用于以条形配置携带功率的互连（引脚，球，焊盘或其他互连），其缩短了功率之间所需的导电路径 源极和半导体器件，并且降低该导电路径的电阻。

公开(公告)号：US20060002098A1

公开(公告)日：2006-01-05

申请号：US11171081

申请日：2005-06-28

Applicant: Robin Berg ,  Todd Husom ,  Derek Sayres

Inventor： Robin Berg ,  Todd Husom ,  Derek Sayres

IPC: H05K7/18

CPC classification number: H04Q1/10 ,  H04Q1/023 ,  H04Q1/03 ,  H04Q1/035 ,  H04Q1/116 ,  H04Q2201/06 ,  H04Q2201/10 ,  H04Q2201/12 ,  H05K1/0216 ,  H05K1/14 ,  H05K1/18 ,  H05K7/1425 ,  H05K7/186 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09354 ,  H05K2201/09663

Abstract: A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The circuit card includes conductor structures such as multiple board layers with paired and segregated conductors. The circuit card also includes some components positioned to cooperate with the ventilation features of the chassis and includes some components chosen for low-power consumption or reduced flammability.