公开(公告)号：US20100230148A1

公开(公告)日：2010-09-16

申请号：US12616891

申请日：2009-11-12

Applicant: Takashi Kariya ,  Daiki Komatsu

Inventor： Takashi Kariya ,  Daiki Komatsu

IPC: H05K1/00 ,  H05K3/00

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5387 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/12044 ,  H05K1/0306 ,  H05K1/144 ,  H05K1/183 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4608 ,  H05K3/4691 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/055 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/063 ,  H01L2224/05599

Abstract: To provide a substrate for mounting a semiconductor element, in which fine-pitch wiring layers are formed to allow a semiconductor element to be mounted, while heat generated in the semiconductor element will not result in a decrease in reliability. Semiconductor-element mounting substrate sandwiches low-thermal-expansion substrate with upper interlayer resin layer and lower interlayer resin layer, and conductive circuit of organic substrate and first conductive circuit of low-thermal-expansion substrate are connected by via conductor formed in interlayer resin layer. Therefore, low-thermal-expansion substrate for mounting semiconductor element may be connected to organic substrate that is connected to outside substrates, without arranging an organic substrate and resin layers on the lower surface of low-thermal-expansion substrate, where impact from the thermal history of semiconductor element is notable.

Abstract translation: 为了提供用于安装半导体元件的基板，其中形成微细间距布线层以允许安装半导体元件，同时在半导体元件中产生的热量不会导致可靠性降低。 半导体元件安装基板将具有上层间树脂层和下层间树脂层的低热膨胀基板夹持，有机基板的导电电路和低热膨胀基板的第一导电电路通过在层间树脂层中形成的通孔导体连接 。 因此，用于安装半导体元件的低热膨胀基板可以连接到与外部基板连接的有机基板，而不在低热膨胀基板的下表面上布置有机基板和树脂层，其中来自热 半导体元件的历史是值得注意的。

公开(公告)号：US07796882B2

公开(公告)日：2010-09-14

申请号：US11507477

申请日：2006-08-22

Applicant: Ho Kyoum Kim ,  Hyoung Woo Nam

Inventor： Ho Kyoum Kim ,  Hyoung Woo Nam

IPC: G03B17/00

CPC classification number: G03B17/02 ,  H01L27/14618 ,  H01L27/14625 ,  H01L31/02164 ,  H01L2924/0002 ,  H04N5/2253 ,  H04N5/2254 ,  H04N5/2257 ,  H05K1/0231 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/09072 ,  H05K2201/10121 ,  H05K2201/10545 ,  Y02P70/611 ,  H01L2924/00

Abstract: The present invention relates to a method of manufacturing an image sensor module including attaching an image sensor on one side of a double-sided flexible printing circuit board (FPCB) provided with a window such that the image sensor module covers the window; and mounting at least one electric part on the other side of the double-sided FPCB on which the image sensor is attached.

Abstract translation: 本发明涉及一种图像传感器模块的制造方法，其包括将图像传感器安装在设置有窗口的双面柔性印刷电路板（FPCB）的一侧，使得图像传感器模块覆盖窗口; 并且在安装有图像传感器的双面FPCB的另一侧上安装至少一个电气部件。

公开(公告)号：US07778041B2

公开(公告)日：2010-08-17

申请号：US11476318

申请日：2006-06-28

Applicant: David Gregory Howell ,  Genn-Sheng Lee

Inventor： David Gregory Howell ,  Genn-Sheng Lee

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/141 ,  H01L2224/73253 ,  H01L2924/13091 ,  H05K1/0203 ,  H05K1/0262 ,  H05K3/3436 ,  H05K2201/10325 ,  H05K2201/10409 ,  H05K2201/10545 ,  H05K2201/1056 ,  H05K2201/10719 ,  H01L2924/00

Abstract: A power interconnection system is provided including a printed circuit board (10), a voltage regulator package (30), and an electrical connection socket (20) adapted for receiving a chip package (40) therein. The electrical socket and the voltage regulator package are mounted and electrically coupled to opposite surfaces of the printed circuit board. Thus, the voltage regulator package and the chip package are held in a substantially opposed relationship relative to the printed circuit board after the chip package is mounted onto the socket. Therefore, with such configuration, a lower impedance connection is achieved between the chip package and the voltage regulator package in comparison with the conventional configuration.

Abstract translation: 提供了一种电源互连系统，包括印刷电路板（10），电压调节器封装（30）和适于在其中容纳芯片封装（40）的电连接插座（20）。 电插座和电压调节器封装被安装并电耦合到印刷电路板的相对表面。 因此，在将芯片封装安装到插座上之后，电压调节器封装和芯片封装相对于印刷电路板保持基本相对的关系。 因此，通过这种配置，与传统配置相比，在芯片封装和电压调节器封装之间实现了较低的阻抗连接。

公开(公告)号：US20100202123A1

公开(公告)日：2010-08-12

申请号：US12697737

申请日：2010-02-01

Applicant: Satoshi Mizuno

Inventor： Satoshi Mizuno

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: A circuit board includes balls as electrodes in a grid, a power supply wiring pattern area connected to power supply terminals of an integrated circuit mounted thereon, and a feeding pattern area connected to a feeding point; the balls include first and second power supply ball groups connected respectively to power supply terminal arrays, at a predetermined interval, of the integrated circuit, and the power supply wiring pattern area includes first and second power supply connection patterns connected respectively to the first and second ball groups, and at least one connection pattern connecting the first and second power supply connection patterns noncontact to the balls, and has first and second connection portions connected respectively to the feeding pattern area and one electrode of a first bypass capacitor, and the second power supply connection pattern has a third connection portion connected to one electrode of a second bypass capacitor.

Abstract translation: 电路板包括作为电网中的电极的球，连接到安装在其上的集成电路的电源端子的电源布线图形区域和连接到馈电点的馈电图案区域; 所述球包括以集成电路的预定间隔分别连接到电源端子阵列的第一和第二电源球组，并且电源布线图案区域包括分别连接到第一和第二电源连接图案的第一和第二电源连接图案 球组，以及将第一和第二电源连接图案连接到球的至少一个连接图案，并且具有分别连接到馈送图案区域和第一旁路电容器的一个电极的第一和第二连接部分，并且第二电力 供电连接图案具有连接到第二旁路电容器的一个电极的第三连接部分。

公开(公告)号：US20100127402A1

公开(公告)日：2010-05-27

申请号：US12692974

申请日：2010-01-25

Applicant: Kevin P. Grundy ,  Joseph C. Fjelstad ,  Gary Yasumura ,  William F. Wiedemann ,  Para K. Segaram

Inventor： Kevin P. Grundy ,  Joseph C. Fjelstad ,  Gary Yasumura ,  William F. Wiedemann ,  Para K. Segaram

IPC: H01L23/48

CPC classification number: H01L23/13 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16235 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/85399 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/182 ,  H05K1/183 ,  H05K3/308 ,  H05K3/3405 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/4046 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0919 ,  H05K2201/092 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10545 ,  H05K2201/1059 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10727 ,  H05K2201/10734 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations.

Abstract translation: 由多个封装，印刷电路板，连接器和插入件采用的结构，以产生减少与使用通孔相关联的有害信号质量问题的信号路径。 公开的结构可以与通孔实现共存。

公开(公告)号：US20100118443A1

公开(公告)日：2010-05-13

申请号：US12588906

申请日：2009-11-02

Applicant: Tetsuya Ohsawa ,  Toshiki Naito

Inventor： Tetsuya Ohsawa ,  Toshiki Naito

IPC: G11B5/48 ,  H05K3/00

CPC classification number: H05K1/189 ,  G11B5/484 ,  G11B5/4853 ,  G11B5/486 ,  H05K1/056 ,  H05K3/305 ,  H05K3/3442 ,  H05K2201/055 ,  H05K2201/09063 ,  H05K2201/09081 ,  H05K2201/10545 ,  H05K2201/10598 ,  Y10T29/49027 ,  Y10T29/49124

Abstract: A suspension board with circuit includes a conductive pattern, a board main body portion on which a magnetic head is mounted, and an auxiliary portion capable of being folded back with respect to the board main body portion so as to face a back surface of the board main body portion. The conductive pattern includes a first conductive pattern including a first terminal electrically connected to an external circuit, and a second terminal electrically connected to the magnetic head, and a second conductive pattern including a third terminal electrically connected to the external circuit, and a fourth terminal electrically connected to an electronic element. Both of the first terminal and the second terminal are disposed on the board main body portion. The third terminal is disposed on the board main body portion or on the auxiliary portion, and the fourth terminal is disposed on the auxiliary portion.

Abstract translation: 具有电路的悬挂板包括导电图案，安装有磁头的板主体部分和能够相对于板主体部分折叠以便面向板的后表面的辅助部分 主体部分。 导电图案包括：第一导电图案，包括电连接到外部电路的第一端子和与磁头电连接的第二端子;以及第二导电图案，其包括电连接到外部电路的第三端子，以及第四端子 电连接到电子元件。 第一端子和第二端子都设置在板主体部分上。 第三端子设置在板主体部分或辅助部分上，第四端子设置在辅助部分上。

公开(公告)号：US07679930B2

公开(公告)日：2010-03-16

申请号：US12245988

申请日：2008-10-06

Applicant: Seiji Hayashi ,  Hideho Inagawa

Inventor： Seiji Hayashi ,  Hideho Inagawa

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0231 ,  H05K1/165 ,  H05K3/429 ,  H05K2201/09263 ,  H05K2201/0949 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract translation: 多层印刷电路板包括：第一表面层，包括半导体集成电路;第二表面层，包括旁路电容器，并且与第一表面层相对;主电源布线层;以及第一表面层， 和第二表面层。 在多层印刷电路板中，旁路电容器的一个端子连接到从主电源布线层到半导体集成电路的电源端子的布线路径的中点，并且从第一布线路径的阻抗 到旁路电容器的端子的主电源布线层高于从旁路电容器的端子到半导体集成电路的电源端子的第二布线路径的阻抗。

公开(公告)号：US20100052802A1

公开(公告)日：2010-03-04

申请号：US12584192

申请日：2009-09-01

Applicant: Junichi Arai

Inventor： Junichi Arai

IPC: H03B1/00

CPC classification number: H03L1/04 ,  H05K1/0206 ,  H05K1/0212 ,  H05K2201/09781 ,  H05K2201/10022 ,  H05K2201/10075 ,  H05K2201/10462 ,  H05K2201/10545 ,  H05K2203/165

Abstract: A constant-temperature type crystal oscillator includes: a crystal unit that is installed on one principal surface of a circuit substrate, and chip resistors, which function as heating elements, and which are installed on the other principal surface of the circuit substrate so as to face a principal surface of the crystal unit, the chip resistors heating up the crystal unit to keep an operational temperature of the crystal unit constant. A heating metal film facing the principal surface of the crystal unit is provided on the one principal surface of the circuit substrate. A heat conducting material is interposed between the principal surface of the crystal unit and the heating metal film to perform thermal coupling therebetween. The heating metal film is thermally coupled to electrode terminals of the chip resistors via a plurality of electrode through holes.

Abstract translation: 恒温型晶体振荡器包括：安装在电路基板的一个主表面上的晶体单元和用作加热元件的片式电阻器，并且安装在电路基板的另一个主表面上，以便 面对晶体单元的主表面，芯片电阻加热晶体单元以保持晶体单元的工作温度恒定。 在电路基板的一个主表面上设置面对晶体单元的主表面的加热金属膜。 导热材料插入在晶体单元的主表面和加热金属膜之间，以在它们之间进行热耦合。 加热金属膜通过多个电极通孔热耦合到芯片电阻器的电极端子。

公开(公告)号：US20100018759A1

公开(公告)日：2010-01-28

申请号：US12356033

申请日：2009-01-19

Applicant: Toshio OE

Inventor： Toshio OE

IPC: H05K1/16

CPC classification number: H05K1/0271 ,  H05K2201/10409 ,  H05K2201/10545 ,  H05K2201/2009 ,  H05K2201/2018

Abstract: According to one embodiment, an electronic device includes a housing, a circuit board housed in the housing, and a reinforcing member. The circuit board has a first surface and a second surface on the rear of the first surface. The first surface has a first electronic component mounted thereon. The second surface has a second electronic component mounted thereon at an opposite position of the first electronic component. The reinforcing member includes a base member and a bridge. The base member is provided on the second surface to reinforce a first mount area on which the first electronic component is mounted. The bridge passes through the first mount area, and extends, across and over the second electronic component, from at least two points on the base member.

Abstract translation: 根据一个实施例，电子设备包括壳体，容纳在壳体中的电路板和加强构件。 电路板在第一表面的后部具有第一表面和第二表面。 第一表面具有安装在其上的第一电子部件。 第二表面具有安装在其上的第二电子元件在第一电子部件的相对位置。 加强构件包括基部构件和桥。 基部构件设置在第二表面上，以加强其上安装有第一电子部件的第一安装区域。 该桥通过第一安装区域，并且从第二电子部件的基底部件上的至少两个点延伸出来。

公开(公告)号：US07608920B2

公开(公告)日：2009-10-27

申请号：US11434964

申请日：2006-05-16

Applicant: James Douglas Wehrly, Jr.

Inventor： James Douglas Wehrly, Jr.

IPC: H01L23/02 ,  H01L21/48 ,  H01L23/04 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/105 ,  G06K19/07732 ,  H01L23/5387 ,  H01L23/5388 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/189 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/2018 ,  H01L2924/00

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allow the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

Abstract translation: 本发明提供一种在存储卡中采用引线封装的存储器件的系统和方法。 引线封装IC布置在柔性电路结构的一侧或两侧以产生IC填充结构。 在优选实施例中，构成引线IC封装的引线被配置为允许引线IC封装的下表面接触柔性电路结构的相应表面。 用于典型实施例的触头由柔性电路结构的刚性部分支撑，并且IC填充结构设置在壳体中以为模块提供卡结构。