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    REMOVAL OF STRESSOR LAYER FROM A SPALLED LAYER AND METHOD OF MAKING A BIFACIAL SOLAR CELL USING THE SAME
    1.
    发明申请
    REMOVAL OF STRESSOR LAYER FROM A SPALLED LAYER AND METHOD OF MAKING A BIFACIAL SOLAR CELL USING THE SAME 审中-公开
    从粉末层去除压力层和使用其制造双极太阳能电池的方法

    公开(公告)号：WO2013181117A3

    公开(公告)日：2014-04-03

    申请号：PCT/US2013042772

    申请日：2013-05-24

    Applicant: IBM

    Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  HEKMATSHOARTABARI BAHMAN ,  LAURO PAUL A ,  LI NING ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD

    IPC: H01L31/18

    CPC classification number: H01L31/0684 ,  H01L21/02002 ,  H01L31/1896 ,  Y02E10/547

    Abstract: A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.

    Abstract translation: 以受控剥落方式使用的应力层通过使用可以断裂或溶解的裂开层去除。 在主体半导体衬底和金属应力层之间形成切割层。 受控的剥落过程将相对薄的残余主体衬底层与主体衬底分离。 在将手柄衬底附接到残留衬底层或随后在其上形成的其它层之后，解理层被溶解或以其他方式受到损害以便于去除应力层。 这种去除允许制造双面太阳能电池。

    DUAL-GATE BIO/CHEM SENSOR
    2.
    发明申请
    DUAL-GATE BIO/CHEM SENSOR 审中-公开
    双门生物/ CHEM传感器

    公开(公告)号：WO2014062285A2

    公开(公告)日：2014-04-24

    申请号：PCT/US2013054601

    申请日：2013-08-13

    Applicant: IBM

    Inventor： BEDELL STEPHEN W ,  HEKMATSHOARTABARI BAHMAN ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD

    IPC: H01L21/336

    CPC classification number: H01L29/78648 ,  H01L21/84

    Abstract: A dual gate extremely thin semiconductor-on-insulator transistor with asymmetric gate dielectrics is provided. This structure can improve the sensor detection limit and also relieve the drift effects. Detection is performed at a constant current mode while the species will be detected at a gate electrode with a thin equivalent oxide thickness (EOT) and the gate bias will be applied to the second gate electrode with thicker EOT to maintain current flow through the transistor. As a result, a small change in the charge on the first electrode with the thin EOT will be translated into a larger voltage on the gate electrode with the thick EOT to sustain the current flow through the transistor. This allows a reduction of the sensor dimension and therefore an increase in the array size. The dual gate structure further includes cavities, i.e., microwell arrays, for chemical sensing.

    Abstract translation: 提供了具有非对称栅极电介质的双栅非常薄的绝缘体上半导体晶体管。 这种结构可以提高传感器的检测极限，也可以减轻漂移的影响。 以恒定电流模式进行检测，同时将在具有薄当量氧化物厚度（EOT）的栅电极处检测物种，并且将栅极偏压施加到具有较大EOT的第二栅电极，以保持电流流过晶体管。 结果，具有薄EOT的第一电极上的电荷的小的变化将被转换成具有较厚EOT的栅电极上的较大电压，以维持通过晶体管的电流。 这允许减小传感器尺寸并因此减小阵列尺寸。 双栅极结构还包括用于化学感测的空腔，即微孔阵列。

    Resistive random access memory integrated with stacked vertical transistors
    3.
    发明专利
    Resistive random access memory integrated with stacked vertical transistors 未知

    公开(公告)号：AU2021234176A1

    公开(公告)日：2022-08-25

    申请号：AU2021234176

    申请日：2021-02-25

    Applicant: IBM

    Inventor： BALAKRISHNAN KARTHIK ,  HEKMATSHOARTABARI BAHMAN ,  REZNICEK ALEXANDER ,  ANDO TAKASHI

    IPC: H01L27/24 ,  H01L29/49 ,  H01L29/66 ,  H01L45/00

    Abstract: A method may include forming two vertical transport field effect transistors stacked one atop the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source (104, 112), a channel (106, 110), and a drain, wherein a contact layer (152) of the resistive random access memory strucure functions as the drain of the two vertical transport field effect transistors. Forming the two vertical transport field effect transistors may further include forming a first source (104) and a second source (112). The first source (104) is a bottom source and the second source (112) is a top source. The method may include forming a gate conductor layer (138, 140) surrounding the channel (106, 110). The resistive random access memory structures may include faceted epitaxy (144) defined by pointed tips. The pointed tips of the faceted epitaxy (144) may extend vertically toward each other. The faceted epitaxy (144) may be between the two vertical transport field effect transistors.

    Back-surface field structures for multi-junction III-V photovoltaic devices
    5.
    发明专利
    Back-surface field structures for multi-junction III-V photovoltaic devices 未知

    公开(公告)号：GB2495828A

    公开(公告)日：2013-04-24

    申请号：GB201218439

    申请日：2012-10-15

    Applicant: IBM

    Inventor： SHAHRJERDI DAVOOD ,  HEKMATSHOARTABARI BAHMAN ,  BEDELL STEPHEN ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM G

    IPC: H01L31/0725 ,  H01L31/076 ,  H01L31/18

    Abstract: A multi-junction III-V photovoltaic device includes a top cell 10 comprised of at least one III-V compound semiconductor material and a bottom cell 16 in contact with a surface of the top cell. The bottom cell includes a germanium-containing layer 18 in contact with the top cell, an intrinsic hydrogenated silicon-containing layer 20 in contact with a surface of the germanium-containing layer, and a doped hydrogenated silicon-containing layer 22 in contact with a surface of the intrinsic hydrogenated silicon-containing layer. The silicon-containing layers, which may be multilayers and can include one or both of germanium and carbon in different proportions, can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline. They provide a back surface field (BSF) structure to the germanium bottom cell to enhance the open circuit voltage of the device. A metallic grid including a plurality of metal fingers 14 and patterned antireflective coatings 12 is located on an upper surface of the top cell 10 and a transparent conductive contact 24 is located on the bottom surface of the bottom cell 16.

    INITIALISIERUNG VON ARBEITSSPEICHER-NETZWERKEN
    6.
    发明专利
    INITIALISIERUNG VON ARBEITSSPEICHER-NETZWERKEN 未知

    公开(公告)号：DE112020005930T5

    公开(公告)日：2022-09-22

    申请号：DE112020005930

    申请日：2020-11-24

    Applicant: IBM

    Inventor： HEKMATSHOARTABARI BAHMAN ,  NAIR RAVI

    IPC: G06N3/063

    Abstract: Ein Arbeitsspeicher-Netzwerk kann mit mindestens Arbeitsspeicher-Schreibgewichtungen, Arbeitsspeicher-Lesegewichtungen und mindestens einem Lesevektor angelegt werden, wobei die Arbeitsspeicher-Schreibgewichtungen Arbeitsspeicher-Schreiboperationen eines neuronalen Netzwerkes für die Arbeitsspeicher-Matrix parametrisieren, wobei die Arbeitsspeicher-Lesegewichtungen Arbeitsspeicher-Leseoperationen des neuronalen Netzwerkes aus der Arbeitsspeicher-Matrix parametrisieren. Mindestens eine der Schreibgewichtungen, der Lesegewichtungen oder Elemente des mindestens einen Lesevektors kann aktualisiert werden, um eine dünne Besetzung und/oder ein Abtastmuster mit niedriger Abweichung zu erhalten. Das Arbeitsspeicher-Netzwerk kann geschult werden, um eine Aufgabe durchzuführen.

    Verfahren zum Bilden einer Tandem-Fotovoltaikeinheit
    9.
    发明专利
    Verfahren zum Bilden einer Tandem-Fotovoltaikeinheit 未知

    公开(公告)号：DE102013211231B4

    公开(公告)日：2016-05-12

    申请号：DE102013211231

    申请日：2013-06-17

    Applicant: IBM

    Inventor： HEKMATSHOARTABARI BAHMAN ,  KHAKIFIROOZ ALI ,  SHAHIDI GHAVAM ,  SHAHRJERDI DAVOOD

    IPC: H01L31/18 ,  H01L31/0236 ,  H01L31/0687 ,  H01L31/0725

    Abstract: Verfahren zum Bilden einer Tandem-Fotovoltaikeinheit, wobei das Verfahren aufweist: Bereitstellen (102) von massivem Germanium oder einer auf einem Siliciumsubstrat gebildeten Germaniumschicht; Nassätzen der Germaniumschicht unter Verwendung eines sauren Ätzmittels, das Phosphorsäure, Wasserstoffperoxid und Ethanol in einem Verhältnis von 1:1:1 enthält; Bilden pyramidenartiger Formen (106; 108) in der Germaniumschicht derart, dass (111)-Kristallflächen (104) freigelegt werden, um eine texturierte Oberfläche zu bilden; Dotieren einer oberen Oberfläche (110) der Germaniumschicht, um einen ersten p-n-Übergang auf oder oberhalb der texturierten Oberfläche zu bilden; Abscheiden einer ersten Halbleiterschicht (112), die der texturierten Oberfläche folgt, auf der oberen Oberfläche, wobei die erste Halbleiterschicht eine GaAs-Schicht oder Legierungen daraus enthält; Dotieren eines Teils der ersten Halbleiterschicht, um einen zweiten p-n-Übergang (132) zu bilden; Abscheiden einer zweiten Halbleiterschicht (116), die dem Profil der texturierten Oberfläche folgt, auf der ersten Halbleiterschicht, wobei die zweite Halbleiterschicht eine GaP-Schicht oder Legierungen daraus enthält; und Dotieren eines Teils der zweiten Halbleiterschicht, um einen dritten p-n-Übergang (134) zu bilden.

    High mobility III-V semiconductor field effect transistors
    10.
    发明专利
    High mobility III-V semiconductor field effect transistors 未知

    公开(公告)号：GB2498854A

    公开(公告)日：2013-07-31

    申请号：GB201300575

    申请日：2013-01-14

    Applicant: IBM

    Inventor： SHAHRJERDI DAVOOD ,  HEKMATSHOARTABARI BAHMAN ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G

    IPC: H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/80

    Abstract: A wide band gap semiconductor buffer layer is incorporated between the channel and an insulating support layer. The conduction band offset of the buffer layer with the channel layer is sufficiently large to confine electron carriers within the channel. The buffer layer also reduces the presence of interface traps, which cause degradation of charge carriers in the channel, caused by the presence of the insulating material. The conduction band offset between the channel layer and the wide bandgap material is between 0.05 eV and 0.8 eV. The channel layer can be comprised of InGaAs or InGaSb with varying compositions of indium and gallium. The wide bandgap material can be comprised of InAlAs AlGaAs or InGaP with varying compositions of indium, aluminium or gallium. The wide bandgap material may comprise an embedded silicon delta-doped layer which provides electrons to the channel layer.

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