公开(公告)号：WO02101834A3

公开(公告)日：2003-05-30

申请号：PCT/GB0202622

申请日：2002-05-30

Applicant: IBM ,  IBM UK

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  MA WILLIAM

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/49

CPC classification number: H01L29/66484 ,  H01L21/2807 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648

Abstract: The present invention features double-or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.

Abstract translation: 本发明的特征在于双栅极或双栅极逻辑器件，其包含始终自对准并且具有恒定宽度的沟道的栅极导体。 本发明的方法还提供了选择性地蚀刻含锗栅极导体材料而不显着蚀刻相邻硅沟道材料的方法。 以这种方式，可以将栅极导体封装在介电壳中，而不改变硅沟道的长度。 采用单晶硅晶片作为通道材料。 自对准双栅极MOSFET的支柱或堆叠通过通过重叠的含锗栅极导体区域的并置进行蚀刻而产生。 通过栅极导电材料和介电绝缘材料的两个区域的垂直蚀刻提供了基本上完美的自对准双栅极叠层。 描述了其中可以选择性地蚀刻栅极导体材料而不蚀刻沟道材料的工艺。

公开(公告)号：WO2007039374A3

公开(公告)日：2007-07-05

申请号：PCT/EP2006065995

申请日：2006-09-05

Applicant: IBM ,  IBM UK ,  HOLMES STEVEN ,  FURUKAWA TOSHIHARU ,  KOBURGER CHARLES III ,  MOUMEN NAIM

Inventor： HOLMES STEVEN ,  FURUKAWA TOSHIHARU ,  KOBURGER CHARLES III ,  MOUMEN NAIM

IPC: G03F7/20 ,  G03F7/11

CPC classification number: G03F7/2041 ,  G03F7/11 ,  G03F7/70341 ,  G03F7/70958

Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

Abstract translation: 提供浸没式光刻系统，其包括可操作以产生具有标称波长的光的光源和光学成像系统。 光学成像系统在从光源到要被图案化的物品的光路中具有光学元件。 光学元件具有适于接触占据面部和物品之间的空间的液体的面。 光学元件包括可通过液体降解的材料和覆盖可降解材料的表面以保护表面免受液体影响的保护涂层，保护涂层对光线是透明的，当暴露于光时稳定并且稳定时 暴露于液体。

公开(公告)号：WO2007039374B1

公开(公告)日：2007-08-30

申请号：PCT/EP2006065995

申请日：2006-09-05

Applicant: IBM ,  IBM UK ,  HOLMES STEVEN ,  FURUKAWA TOSHIHARU ,  KOBURGER CHARLES III ,  MOUMEN NAIM

Inventor： HOLMES STEVEN ,  FURUKAWA TOSHIHARU ,  KOBURGER CHARLES III ,  MOUMEN NAIM

IPC: G03F7/20 ,  G03F7/11

CPC classification number: G03F7/2041 ,  G03F7/11 ,  G03F7/70341 ,  G03F7/70958

Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

Abstract translation: 提供了一种浸没光刻系统，其包括可操作以产生具有标称波长的光和光学成像系统的光源。 光学成像系统具有从光源到待图案化的制品的光路中的光学元件。 光学元件具有适于接触占据面部和制品之间的空间的液体的面。 光学元件包括可被液体降解的材料和覆盖面上的可降解材料以保护面部免受液体的保护涂层，保护涂层对于光是透明的，当暴露于光时稳定，并且当稳定时 暴露于液体。

公开(公告)号：WO2011080016A2

公开(公告)日：2011-07-07

申请号：PCT/EP2010068318

申请日：2010-11-26

Applicant: IBM ,  SANDERS DANIEL PAUL ,  CHENG JOY ,  HINSBERG WILLIAM ,  KIM HO-CHEOL ,  COLBURN MATTHEW ,  HARRER STEFAN ,  HOLMES STEVEN

Inventor： SANDERS DANIEL PAUL ,  CHENG JOY ,  HINSBERG WILLIAM ,  KIM HO-CHEOL ,  COLBURN MATTHEW ,  HARRER STEFAN ,  HOLMES STEVEN

IPC: G03F7/00

CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

Abstract: A method of forming a layered structure comprising a self-assembled material comprises: disposing a non-crosslinking photoresist layer on a substrate; pattern-wise exposing the photoresist layer to first radiation; optionally heating the exposed photoresist layer; developing the exposed photoresist layer in a first development process with an aqueous alkaline developer, forming an initial patterned photoresist layer; treating the initial patterned photoresist layer photochemically, thermally and/or chemically, thereby forming a treated patterned photoresist layer comprising non-crosslinked treated photoresist disposed on a first substrate surface; casting a solution of an orientation control material in a first solvent on the treated patterned photoresist layer, and removing the first solvent, forming an orientation control layer; heating the orientation control layer to effectively bind a portion of the orientation control material to a second substrate surface; removing at least a portion of the treated photoresist and, optionally, any non-bound orientation control material in a second development process, thereby forming a pre-pattern for self-assembly; optionally heating the pre-pattern; casting a solution of a material capable of self-assembly dissolved in a second solvent on the pre-pattern and removing the second solvent; and allowing the casted material to self-assemble with optional heating and/or annealing, thereby forming the layered structure comprising the self-assembled material.

Abstract translation: 形成包括自组装材料的层状结构的方法包括：在基底上设置非交联光致抗蚀剂层; 将光致抗蚀剂层图案化地暴露于第一辐射; 可选地加热曝光的光致抗蚀剂层; 在第一显影工艺中用含水碱性显影剂显影曝光的光致抗蚀剂层，形成初始图案化的光致抗蚀剂层; 以光学，光学和/或化学方式处理初始图案化的光致抗蚀剂层，从而形成经处理的图案化的光刻胶层，其包含设置在第一衬底表面上的非交联处理的光致抗蚀剂; 在经处理​​的图案化光刻胶层上浇铸取向控制材料在第一溶剂中的溶液，并除去第一溶剂，形成取向控制层; 加热所述取向控制层以有效地将所述取向控制材料的一部分粘合到第二基板表面; 在第二显影过程中除去至少一部分经处理的光致抗蚀剂和任选的任何未结合的取向控制材料，从而形成用于自组装的预图案; 可选地加热预图案; 将能够自组装的溶解在第二溶剂中的材料的溶液浇铸在预图案上并除去第二溶剂; 并且允许铸造材料通过任选的加热和/或退火自组装，从而形成包括自组装材料的层状结构。

公开(公告)号：AU2021236824A1

公开(公告)日：2022-07-28

申请号：AU2021236824

申请日：2021-02-16

Applicant: IBM

Inventor： HOLMES STEVEN ,  SADANA DEVENDRA ,  GLUSCHENKOV OLEG

IPC: H01L39/02 ,  H01L39/12 ,  H01L39/22 ,  H01L39/24

Abstract: According to an embodiment of the present invention, a quantum mechanical device includes a monolithic crystalline structure. The monolithic crystalline structure includes a first region doped to provide a first superconducting region, and a second region doped to provide a second superconducting region, the second superconducting region being separated from the first superconducting region by an undoped crystalline region. The first and second superconducting regions and the undoped crystalline region form a Josephson junction.

公开(公告)号：SG11201404867YA

公开(公告)日：2014-09-26

申请号：SG11201404867Y

申请日：2013-06-27

Applicant: IBM

Inventor： CHEN KUANG-JUNG ,  HOLMES STEVEN ,  HUANG WU-SONG ,  KWONG RANEE WAI-LING ,  LIU SEN

IPC: G02B1/11 ,  B32B7/02 ,  G03F7/004

Abstract: The present invention relates to a developable bottom antireflective coating (BARC) composition and a pattern forming method using the BARC composition. The BARC composition includes a first polymer having a first carboxylic acid moiety, a hydroxy-containing alicyclic moiety, and a first chromophore moiety; a second polymer having a second carboxylic acid moiety, a hydroxy-containing acyclic moiety, and a second chromophore moiety; a crosslinking agent; and a radiation sensitive acid generator. The first and second chromophore moieties each absorb light at a wavelength from 100 nm to 400 nm. In the patterning forming method, a photoresist layer is formed over a BARC layer of the BARC composition. After exposure, unexposed regions of the photoresist layer and the BARC layer are selectively removed by a developer to form a patterned structure in the photoresist layer. The BARC composition and the pattern forming method are especially useful for implanting levels.

公开(公告)号：GB2485941B

公开(公告)日：2014-05-21

申请号：GB201203971

申请日：2010-11-26

Applicant: IBM

Inventor： SANDERS DANIEL PAUL ,  CHENG JOY ,  HINSBERG WILLIAM ,  KIM HO-CHEOL ,  COLBURN MATTHEW ,  HARRER STEFAN ,  HOLMES STEVEN

IPC: G03F7/00

Abstract: A layered structure comprising a self-assembled material is formed by a method that includes forming a photochemically, thermally and/or chemically treated patterned photoresist layer disposed on a first surface of a substrate. The treated patterned photoresist layer comprises a non-crosslinked treated photoresist. An orientation control material is cast on the treated patterned photoresist layer, forming a layer containing orientation control material bound to a second surface of the substrate. The treated photoresist and, optionally, any non-bound orientation control material are removed by a development process, resulting in a pre-pattern for self-assembly. A material capable of self-assembly is cast on the pre-pattern. The casted material is allowed to self-assemble with optional heating and/or annealing to produce the layered structure.

公开(公告)号：GB2487309B

公开(公告)日：2014-03-19

申请号：GB201201714

申请日：2010-10-19

Applicant: IBM

Inventor： DORIS BRUCE ,  ZHANG YING ,  CHENG KANGGUO ,  HOLMES STEVEN ,  HUA XUEFENG

IPC: H01L21/033 ,  H01L21/308

Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

公开(公告)号：AT438926T

公开(公告)日：2009-08-15

申请号：AT02796462

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  LEAS JAMES ,  MA WILLIAM ,  RABIDOUX PAUL

IPC: H01L29/76 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

公开(公告)号：AT416399T

公开(公告)日：2008-12-15

申请号：AT06793243

申请日：2006-09-05

Applicant: IBM

Inventor： KOBURGER III ,  HOLMES STEVEN ,  HORAK DAVID ,  KIMMEL KURT ,  PETRILLO KAREN ,  ROBINSON CHRISTOPHER

IPC: G03F7/20

Abstract: An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.