公开(公告)号：MY127563A

公开(公告)日：2006-12-29

申请号：MYPI20020088

申请日：2002-01-11

Applicant: IBM

Inventor： BALLANTINE ARNE W ,  GROVES ROBERT A ,  LUND JENNIFER L ,  NAKOS JAMES S ,  RICE MICHAEL B ,  STAMPER ANTHONY K

IPC: H01L21/768 ,  H01L29/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/822 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A METHOD AND STURCTURE THAT PROVIDES A BATTERY (420) WITHIN AN INTEGRATED CIRCUIT (400) FOR PROVIDING VOLTAGE TO LOW-CURRENT ELECTRONIC DEVICES (900) THAT EXIST WITHIN THE INTERGRATED CIRCUIT. THE METHOD INCLUDES FRONT-END-OF-LINE (FEOL) PROCESSING FOR GENERATING A LAYER OF ELECTRONIC DEVICES ON A SEMICONDUCTOR WAFER (402), FOLLOWED BY BACK-END-OF-LINE(BEOL) INTEGRATION FOR WIRES THE BEOL INTEGRATION INCLUDES FORMING A MULTILAYERED STRUCTURE OF WIRING LEVELS ON THE LAYER OF ELECTORINC DEVICES. EACH WIRING LEVEL INCLUDES CONDUCTIVE METALLIZATION (E.G., METAL-PLATED VIAS CONDUCTIVE WIRING LINES, ETC) EMBEDDED IN INSULATIVE MATERIAL. THE BATTERY IS FORMED DURING BEOL INTEGRATION WITHIN ONE OR MORE WIRING LEVELS, AND THE CONDUCTIVE METALLIZATION (432,434,442,444)(E.G.,METAL-PALTED VIAS,CONDUCTIVE WIRING LINES, ETC.)EMBEDDED IN INSULATIVE MATERIAL.THE BATTERY IS FORMED DURING BEOL INTEGRATION WITHIN ONE OR MORE WIRING LEVELS,AND THE CONDUCTIVE METALLIZATION CONDUCTIVELY COUPLE POSITIVE (424) AND NEGATIVE (422) TERMINALS OF THE BATERRY TO THE ELECTRONIC DEVICES.THE BATERRY MAY HAVE SEVERAL DIFFERENT TOPOLOGIES RELATIVE TO THE STRUCTURAL AND GEOMETRICAL RELATIONSHIPS AMONG THE BATERRY ELECTRODES AND ELECTROLYTE.MULTIPLE BATTERIES MAY BE FORMED WITHIN ONE OR MORE WIRING LEVELS,AND MAY BE CONDUCTIVELY COUPLE TO THE ELECTRONIC DEVICES.THE MULTIPLE BATERIES MAY BE CONNECTED IN SERIES OR IN PARALLEL.(FIG.1)

公开(公告)号：CA2514454A1

公开(公告)日：2004-08-19

申请号：CA2514454

申请日：2004-01-23

Applicant: IBM

Inventor： SIMON ANDREW H ,  GEFFKEN ROBERT M ,  MARINO JEFFREY R ,  COONEY EDWARD C III ,  STAMPER ANTHONY K

IPC: H01L21/768

Abstract: A semiconductor device which includes an improved liner structure formed in a via having extended sidewall portions and a bottom penetrating a metal line. The liner structure includes two liner layers, the first being on the via sidewalls, but not the bottom, and the second being on the first layer and the extended sidewall portions and bottom of the via. A method of making the liner structure, in which the first layer is deposited prior to an etching or cleaning step, which extends the via into the metal line, is also disclosed.

公开(公告)号：MY117252A

公开(公告)日：2004-06-30

申请号：MYPI9800951

申请日：1998-03-04

Applicant: IBM

Inventor： CRONIN JOHN E ,  HARTSWICK THOMAS J ,  STAMPER ANTHONY K

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/42 ,  H01L23/522 ,  H01L23/532 ,  H01L27/01 ,  H01L29/40

Abstract: THE PREFERRED EMBODIMENT OF THE PRESENT INVENTION PROVIDES INCREASED CONDUCTIVITY BETWEEN INTERLEVEL INTERCONNECTION LINES (104, 304, 521). THE PREFERRED EMBODIMENT USES SIDEWALL SPACERS (120, 122,320,322,520, 522) ON THE SIDES OF THE INTERCONNECTION LINES TO INCREASE THE CONTACT AREA BETWEEN INTERCONNECTION LINES AND INTERCONNECT STUDS (102). THIS INCREASE IN AREA IMPROVES CONNECTION RESISTANCE AND ALLOWS FURTHER DEVICE SCALING WITHOUT UNACCEPTABLE DECREASES IN THE CONDUCTIVITY OF THE CONNECTION, AND WITHOUT ADDING SIGNIFICANT EXPENSE IN THE FABRICATION PROCESS.

公开(公告)号：AU2002346512A1

公开(公告)日：2003-07-30

申请号：AU2002346512

申请日：2002-11-22

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K ,  WANG YUN YU ,  KALTALIOGLU ERDEM ,  CHEN TZE-CHIANG ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

公开(公告)号：SG65024A1

公开(公告)日：1999-05-25

申请号：SG1997003669

申请日：1997-10-06

Applicant: IBM

Inventor： COONEY EDWARD C III ,  LEE HYUN K ,  MCDEVITT THOMAS L ,  STAMPER ANTHONY K

IPC: H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/56

Abstract: Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.