公开(公告)号：DE19860084B4

公开(公告)日：2005-12-22

申请号：DE19860084

申请日：1998-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINRICH VOLKER ,  ENGELHARDT MANFRED ,  KREUPL FRANZ ,  SCHIELE MANUELA ,  SAENGER ANNETTE ,  HARTNER WALTER

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/304

公开(公告)号：DE19640238B4

公开(公告)日：2005-04-14

申请号：DE19640238

申请日：1996-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESPEJO-MAZURE CARLOS ,  SCHINDLER GUENTHER ,  HARTNER WALTER

IPC: H01L27/115 ,  H01L27/11502 ,  H01L27/105 ,  H01L21/8239

公开(公告)号：DE59709642D1

公开(公告)日：2003-04-30

申请号：DE59709642

申请日：1997-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  HARTNER WALTER ,  HINTERMAIER FRANK ,  MAZURE-ESPEJO CARLOS ,  BRUCHHAUS RAINER ,  HOENLEIN WOLFGANG ,  ENGELHARDT MANFRED

IPC: H01L27/10 ,  H01G4/00 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11502

Abstract: The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

公开(公告)号：DE10131627A1

公开(公告)日：2003-01-30

申请号：DE10131627

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239 ,  H01L27/105

Abstract: Semiconductor memory has capacitor devices (10-1,...., 10-4) each vertically extending from a substrate (20) and/or a passivating region (21) and/or a surface region (20a). A three dimensional arrangement or structure is formed for each capacitor device. An Independent claim is also included for a process for the production of a semiconductor memory. Preferred Features: The capacitor devices each have a first electrode arrangement (14), a second electrode arrangement (18) with a dielectric (16) arranged between the arrangements. The capacitor devices are a stacked structure of form part of a stacked structure.

公开(公告)号：DE10131624A1

公开(公告)日：2003-01-23

申请号：DE10131624

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/105 ,  H01L21/8239

Abstract: A method for manufacturing a semiconductor memory device, in which a semiconductor substrate (20) a passivation zone (21) and/or a surface zone (20a, 21a) are designed with a CMOS structure. The capacitor device (10-1...10-4) is structured mainly in the horizontally-extending semiconductor substrate or similar of a passivation zone (21) and/or a surface zone from it, at least partly and/or locally structured and mainly vertically formed. A passivation zone (21) and/or a surface zone (20a, 21a) is formed and/or structured at least partly in the arrangement or structure extending in the third dimension for the respective capacitor device (10-1...10-4). An Independent claim is given for a chain-FeRAM store. (B)

公开(公告)号：DE10131492A1

公开(公告)日：2003-01-16

申请号：DE10131492

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: G11C7/00 ,  H01L21/02 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: Production of a semiconductor device comprises forming and/or structuring capacitor arrangements (10-1, ..., 10-4) on a semiconductor substrate (20), a passivating region (21) and/or surface region (20a, 21a), and forming a three-dimensional arrangement for the capacitor arrangements. An Independent claim is also included for the semiconductor device produced by the above process. Preferred Features: Electrode arrangements (14, 18) and a dielectric (16) of each capacitor arrangement are formed and/or structured on the substrate, passivating region and/or surface region.

公开(公告)号：DE10125370C1

公开(公告)日：2002-11-14

申请号：DE10125370

申请日：2001-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  MOERT MANFRED ,  SCHINDLER GUENTHER ,  WEINRICH VOLKER

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8239

Abstract: The manufacturing method has a dielectric or ferroelectric layer for integrated capacitors (2) of the semiconductor circuit deposited on an intermediate carrier, which is heated for conversion of the dielectric or ferroelectric layer into a highly polarized phase. The dielectric or ferroelectric layer is subsequently released from the intermediate carrier and reduced into small particles (4) applied to the semiconductor substrate (1) for the semiconductor circuit.

公开(公告)号：DE19963500C2

公开(公告)日：2002-10-02

申请号：DE19963500

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER ,  WEINRICH VOLKER ,  AHLSTEDT MATTIAS

IPC: H01L21/316 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L21/321 ,  C23C14/08 ,  C23C16/40

Abstract: The damage to edge sections which occurs during the patterning of a metal-oxide-containing layer can be compensated by the deposition of an annealing layer and a subsequent heat treatment step through which a material flow takes place from the annealing layer into the damaged edge sections. The metal-oxide-containing layer can form the dielectric of a storage capacitor of a DRAM memory cell.

公开(公告)号：DE10041685C2

公开(公告)日：2002-06-27

申请号：DE10041685

申请日：2000-08-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER ,  GABRIC ZVONIMIR

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L21/8239

Abstract: Production of a microelectronic component comprises: (i) forming a storage capacitor containing a first electrode, a second electrode and a ferroelectric or paraelectric dielectric on a substrate; and (ii) forming a barrier on the capacitor to prevent the hydrogen passing through. The hydrogen barrier is produced by forming a silicon oxide layer (41), tempering the capacitor and at least a part of the silicon oxide layer, and applying a barrier layer (42) to the tempered silicon oxide layer. Preferred Features: At least a part of the barrier layer is applied in a hydrogen-free deposition process. A first partial layer of the barrier layer is initially applied followed by a second partial layer of silicon nitride. The silicon nitride layer is deposited using a low pressure microwave process. The silicon oxide layer has partial layers (411, 412).

公开(公告)号：DE10056295A1

公开(公告)日：2002-05-23

申请号：DE10056295

申请日：2000-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  GABRIC ZVONIMIR ,  KROENKE MATTHIAS ,  SCHINDLER GUENTER

IPC: H01L21/02 ,  H01L21/285 ,  H01L27/115 ,  H01L27/11502 ,  H01L21/8239

Abstract: Production of a ferroelectric capacitor comprises inserting a ferroelectric or para-electric material as dielectric (6) between precious metal electrodes (3, 4) of the capacitor (1); and depositing a TaSixNy layer as hydrogen diffusion barrier (7) over the capacitor to protect the ferroelectric or para-electric material from hydrogen used in the integration process. An Independent claim is also included for a highly integrated non-volatile storage capacitor. Preferred Features: The TaSixNy layer is structured so that it lies between an electrode plate of the capacitor and a Ti/TiN barrier layer in a neighboring through-hole filled with tungsten.