公开(公告)号：US20100139963A1

公开(公告)日：2010-06-10

申请号：US12654017

申请日：2009-12-08

Applicant: Kiminori Ishido

Inventor： Kiminori Ishido

IPC: H05K1/16 ,  H05K1/11 ,  B05D5/12 ,  C23F1/00

CPC classification number: H05K1/111 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/099 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124 ,  H01L2224/0401

Abstract: Embodiments of the invention provide an interconnect substrate capable of improving the connection reliability and yield of a semiconductor device, a method of manufacturing the interconnect substrate, and a semiconductor device using the interconnect substrate.An interconnect substrate according to an embodiment of the invention includes: a substrate; an electrode pad formed over the substrate; an insulating film (solder resist film) formed over the substrate; an opening formed in the insulating film, in which the upper surface of the electrode pad is exposed on the bottom surface of the opening; and a metal film formed over the upper surface of the electrode pad and side surface of the insulating film in the opening. At least a portion of the edge of an upper surface of the metal film is higher than the other portions of the upper surface of the metal film.

Abstract translation: 本发明的实施例提供能够提高半导体器件的连接可靠性和产量的互连基板，制造互连基板的方法以及使用该互连基板的半导体器件。 根据本发明实施例的互连衬底包括：衬底; 形成在所述基板上的电极焊盘; 形成在基板上的绝缘膜（阻焊膜） 形成在绝缘膜上的开口，其中电极焊盘的上表面暴露在开口的底表面上; 以及形成在电极焊盘的上表面和开口中的绝缘膜的侧表面上的金属膜。 金属膜的上表面的边缘的至少一部分高于金属膜的上表面的其它部分。

公开(公告)号：US20090255111A1

公开(公告)日：2009-10-15

申请号：US12488638

申请日：2009-06-22

Applicant: Michimasa Takahashi ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

IPC: H05K3/00

CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09863 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/31511

Abstract: A method of forming a circuit board which includes generating laser light with a carbon dioxide laser and making a hole through an insulating substrate by irradiating the insulating substrate with the laser light. The hole includes a top opening in a top surface of the insulating substrate, a bottom opening in a bottom surface of the insulating substrate, and an inner wall extending from the top opening to the bottom opening along a thickness direction of the insulating substrate, the inner wall including a bulge which extends in a direction generally orthogonal to the thickness direction. A via hole is formed in the insulating substrate by providing metal in the hole such that the metal extends from the top opening to the bottom opening along the inner wall, and completely closes each of the top and bottom openings.

Abstract translation: 一种形成电路板的方法，其包括用二氧化碳激光器产生激光并通过用激光照射绝缘基板使绝缘基板形成孔。 所述孔包括在所述绝缘基板的上表面中的顶部开口，所述绝缘基板的底表面中的底部开口以及沿着所述绝缘基板的厚度方向从所述顶部开口延伸到所述底部开口的内壁， 内壁包括在大致正交于厚度方向的方向上延伸的凸起。 通过在孔中提供金属使得金属沿着内壁从顶部开口延伸到底部开口，并且完全封闭每个顶部和底部开口，在绝缘基板中形成通孔。

公开(公告)号：US20080017410A1

公开(公告)日：2008-01-24

申请号：US11866163

申请日：2007-10-02

Applicant: Miguel Jimarez ,  Ross Keesler ,  Voya Markovich ,  Rajinder Rai ,  Cheryl Tytran-Palomaki

Inventor： Miguel Jimarez ,  Ross Keesler ,  Voya Markovich ,  Rajinder Rai ,  Cheryl Tytran-Palomaki

IPC: H01L21/02 ,  H05K1/00

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/3484 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09863 ,  H05K2203/043 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for forming a plated microvia interconnect. An external dielectric layer (EDL) is mounted on a substrate in direct mechanical contact with a conductive element thereon. An opening in the EDL exposes the conductive element and create a microvia in the EDL. A sidewall and bottom wall surface of the microvia are treated to promote adhesion of copper and are plated with a layer of copper that includes a copper layer on a copper seed layer and is in direct mechanical and electrical contact with the conductive element. A wet solder paste is deposited on the layer of copper to overfill a remaining portion of the microvia. The solder paste is reflowed to form a solder bump in and over the remaining portion of the microvia to form the plated microvia interconnect. A stiffener is attached to the EDL using a first adhesive.

Abstract translation: 一种形成电镀微孔互连的方法。 外部电介质层（EDL）安装在基板上，与其上的导电元件直接机械接触。 EDL中的一个开口暴露了导电元件，并在EDL中创建了微孔。 处理微孔的侧壁和底壁表面以促进铜的粘附，并在铜籽晶层上镀一层包含铜层的铜层，并与导电元件直接机械和电接触。 在铜层上沉积湿焊膏，以过量填充微孔的剩余部分。 焊膏被回流以在微孔的剩余部分中和上方形成焊料凸块以形成电镀微孔互连。 使用第一粘合剂将加强件附接到EDL。

公开(公告)号：US20070146974A1

公开(公告)日：2007-06-28

申请号：US11318033

申请日：2005-12-23

Applicant: Cleopatra Cabuz ,  Eugen Cabuz ,  Tzu-Yu Wang

Inventor： Cleopatra Cabuz ,  Eugen Cabuz ,  Tzu-Yu Wang

IPC: H05K5/00

CPC classification number: H05K3/107 ,  H05K1/0284 ,  H05K3/046 ,  H05K3/146 ,  H05K3/16 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09127 ,  H05K2201/09836 ,  H05K2201/09863

Abstract: A method of forming an electronic part having a circuit pattern, by forming a cavity mold having trench lines in the cavity mold with a first area perpendicular to an axis and a second area having a negative slope with respect to the axis. The part is molded and removed, and a conductive material is deposited to form conductive and nonconductive areas thereon. The preferred deposit step is by blanket metallization which coats all surfaces except the sides of the trench lines and the second area of the part. The method may include the additional step of molding vertical flash portions on the part instead of or in addition to the trench lines that are removed after the conductive material is deposited thereon to form the circuit pattern.

Abstract translation: 一种形成具有电路图形的电子部件的方法，通过在空腔模具中形成具有沟槽线的空腔模具，其具有垂直于轴线的第一区域和相对于该轴线具有负斜率的第二区域。 该部件被模制和去除，并且沉积导电材料以在其上形成导电和非导电区域。 优选的沉积步骤是通过覆盖金属化，其涂覆除了沟槽线的侧面和部分的第二区域之外的所有表面。 该方法可以包括在导电材料沉积在其上以形成电路图案之后，在部分上成型垂直闪光部分的附加步骤，而不是或除了沟槽线之外去除的导电材料。

公开(公告)号：US20060283625A1

公开(公告)日：2006-12-21

申请号：US11452933

申请日：2006-06-15

Applicant: Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Kenta Ogawa ,  Jun Tsukano ,  Hirokazu Honda

Inventor： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Kenta Ogawa ,  Jun Tsukano ,  Hirokazu Honda

IPC: H05K1/11 ,  H05K1/03

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K3/0055 ,  H05K3/20 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/09863 ,  H05K2203/0796 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.

Abstract translation: 在由板状绝缘膜的一面形成的凹部形成有由布线体和蚀刻阻挡层构成的下层布线的布线基板，在基板绝缘膜的另一面形成有上层布线， 绝缘膜，上层布线和下层布线的布线体通过形成在基板绝缘膜上的通孔相互连接。 通孔为桶形，钟形或波纹管状。

公开(公告)号：US06998291B2

公开(公告)日：2006-02-14

申请号：US10859639

申请日：2004-06-03

Applicant: Shigetsugu Muramatsu ,  Tohru Hizume

Inventor： Shigetsugu Muramatsu ,  Tohru Hizume

IPC: H01L21/44

CPC classification number: H05K3/4644 ,  H05K3/005 ,  H05K3/421 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0108 ,  H05K2203/1189

Abstract: A wiring board is disclosed that includes a first insulating layer, a conductor which is formed on a surface of the first insulating layer, and a second insulating layer which is formed on surfaces of the first insulating layer and of the conductor. The wiring board is provided with a semispherical-shaped or conical-shaped hole-forming portion which penetrates through the second insulating layer into the conductor.

Abstract translation: 公开了一种布线板，其包括第一绝缘层，形成在第一绝缘层的表面上的导体和形成在第一绝缘层和导体的表面上的第二绝缘层。 布线板设置有半球形或圆锥形的孔形成部分，其穿过第二绝缘层进入导体。

公开(公告)号：US20040025333A1

公开(公告)日：2004-02-12

申请号：US10356464

申请日：2003-02-03

Applicant: IBIDEN Co., Ltd.

Inventor： Naohiro Hirose ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

IPC: H05K003/36 ,  H05K003/20

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 nullm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Abstract translation: 通过激光束在树脂20中形成开口，从而形成通孔。 此时，通过进行蚀刻来降低导热率的铜箔22的厚度（3μm）被用作保形掩模。 因此，如果脉冲形激光束的照射次数减少，则可以在树脂20中形成开口20a。 因此，可以防止形成层间绝缘树脂层的树脂20的底切的发生。 因此，可以提高通孔连接的可靠性。

公开(公告)号：US06581280B2

公开(公告)日：2003-06-24

申请号：US10197125

申请日：2002-07-17

Applicant: Brian Eugene Curcio ,  Peter Alfred Gruber ,  Frederic Maurer ,  Konstantinos I. Papathomas ,  Mark David Poliks

Inventor： Brian Eugene Curcio ,  Peter Alfred Gruber ,  Frederic Maurer ,  Konstantinos I. Papathomas ,  Mark David Poliks

IPC: H05K330

CPC classification number: H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/53191 ,  H01L2924/00

Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.

Abstract translation: 提供介电基片中的高纵横比（5：1-30：1）和小（5毫米-125毫米）直径的孔，填充有凝固的导电材料，以及使用压力填充这些孔的方法 和真空。 在某些实施例中，孔用导电材料衬里和/或用导电材料封盖。 本发明还考虑由这种材料形成的芯片载体。

公开(公告)号：US06571467B2

公开(公告)日：2003-06-03

申请号：US09358365

申请日：1999-07-21

Applicant: Takayuki Haze ,  Tsuneo Yabuuchi

Inventor： Takayuki Haze ,  Tsuneo Yabuuchi

IPC: H01K310

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/385 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/086 ,  H05K2203/087 ,  H05K2203/1157 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49165

Abstract: The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.

Abstract translation: 一种制造印刷电路板的方法，包括以下步骤：制备导电基板，在所述基板的一个表面上形成绝缘层，在绝缘层中形成至少一个通孔，热固化绝缘层，并至少减少 在固化操作期间在基板的另一导电表面上形成一个氧化层。 或者，热固化可以在不利于金属化电路表面上的氧化物形成的气氛（例如还原气体，惰性气体或其混合物）中完成。

公开(公告)号：US20020175438A1

公开(公告)日：2002-11-28

申请号：US10191378

申请日：2002-07-08

Applicant: International Business Machines Corporation

Inventor： Peter A. Gruber ,  Frederic Maurer ,  Lubomyr Taras Romankiw

IPC: B29C045/14 ,  B29C045/63

CPC classification number: H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  H01L2924/00

Abstract: An apparatus and a method for filling high aspect ratio holes in electronic substrates that can be advantageously used for filling holes having aspect ratios larger than 5:1 are disclosed. In the apparatus, a filler plate and a vacuum plate are used in conjunction with a connection means such that a gap is formed between the two plates to accommodate an electronic substrate equipped with high aspect ratio via holes. The filler plate is equipped with an injection slot while the vacuum plate is equipped with a vacuum slot such that when a substrate is sandwiched therein, via holes can be evacuated of air and injected with a liquid simultaneously from a bottom side and a top side of the substrate. The present invention novel apparatus and method allows the filling of via holes that have small diameters, i.e., as small as 10 nullm, and high aspect ratios, i.e., at least 5:1 to be filled with an electrically conductive material such as a solder or a conductive polymer such that vias or interconnects can be formed in electronic substrates. The present invention apparatus and method can be advantageously used in fabricating substrates for display panels by forming conductive vias and interconnects for placing a voltage potential on pixel display elements formed on the display panels.

Abstract translation: 公开了一种用于填充电子基板中的高纵横比孔的装置和方法，其可以有利地用于填充具有大于5:1的纵横比的孔。 在装置中，填充板和真空板与连接装置结合使用，使得在两个板之间形成间隙以容纳配备有高纵横比通孔的电子基板。 填充板配备有注入槽，而真空板配备有真空槽，使得当基板夹在其中时，通孔可以从空气排出并同时从液体的底侧和顶侧注入液体 底物。 本发明的新型装置和方法允许填充具有小直径，即小至10um，高纵横比，即至少5:1的通孔，以填充诸如焊料的导电材料 或导电聚合物，使得可以在电子基板中形成通孔或互连。 本发明的装置和方法可以有利地用于制造用于显示面板的基板，通过形成用于在形成在显示面板上的像素显示元件上放置电压电位的导电通孔和互连。