公开(公告)号：JPH07235642A

公开(公告)日：1995-09-05

申请号：JP29764694

申请日：1994-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PADOAN SILVIA ,  GOLLA CARLA

IPC: H01L27/04 ,  G05F3/24 ,  H01L21/822

Abstract: PURPOSE: To provide a circuit configuration which can supply, with a highly simple arrangement, an accurate and stable reference potential and at the same time, can stabilize the power supply, even when temperature and process parameters vary. CONSTITUTION: This circuit includes at least one field effect transistor (M1) 103 and a resistive bias element (R) 102, connected in series with a supply power VCC between the supply power and ground, and a second field effect transistor (M2) 104 connected to the transistor 103 in such a manner that a reference potential can be extracted as a difference between the threshold voltages of the 2 transistors.

公开(公告)号：JPH07220490A

公开(公告)日：1995-08-18

申请号：JP32565394

申请日：1994-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CASAGRANDE GIULIO ,  CAMERLENGHI EMILIO

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

Abstract: PURPOSE: To make the voltage drop of a circuit element the function of the actual length of a memory cell by incorporating the circuit element to a voltage adjuster. CONSTITUTION: The voltage adjuster 3 is provided with a gain stage, which is provided with an input terminal connected to the voltage divider 6 of a programming voltage VPP and an output terminal U connected with the programming line 5 of at least one memory cell 2 and supplied with programming voltage VPP. In addition at least one circuit element 4 compensating the fluctuation of a percentage by a programming line voltage for the length of the memory cell 2 is provided.

公开(公告)号：JPH07218578A

公开(公告)日：1995-08-18

申请号：JP2865295

申请日：1995-01-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PENZA LUIGI ,  FAVALLI MICHELE ,  RICCO BRUNO

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  H01L21/66

Abstract: PURPOSE: To evaluate the existence of resistant bridging defect by sensing that voltages existing in one or more signal nodes stay within a predetermined intermediate voltage range. CONSTITUTION: An AUX-LINE is connected to one of two supply lines VDD of a functional CMOS or BiCMOS cell of an integrated circuit, or an earth via a load. Respective inverter stages which are input from the output node of a logic cell to be traced are connected to the AUX-LINE and the other of the two lines VDD, and are made of (n) channel and (r) channel transistors. When the voltage of the output node of the logic cell has middle level within a predetermined intermediate voltage range, the respective inverter stages cause the AUX-LINE and the other line VDD to be conductive mutually so that the voltage of the output node can be traced. By matching the trigger levels of the respective inverter stages with the logic threshold level of the logic cell, the accurate selection test of the logic cell can be executed.

公开(公告)号：JPH07184237A

公开(公告)日：1995-07-21

申请号：JP26730394

申请日：1994-10-31

Applicant: ST MICROELECTRONICS SRL

Inventor： TORAZZINA ALDO

IPC: H04M1/00 ,  H04M1/654 ,  H04M1/738 ,  H04Q3/42

Abstract: PURPOSE: To reduce the cost of a device and the area required for integration of a circuit and to improve the reliability of the device by reducing the number of parts. CONSTITUTION: A single photo coupler 3 is provided which has an input terminal connected to a terminal of a telephone line and is connected to a transmission circuit for call signal transmission connected between two terminals of the telephone line and is connected to the output terminal of a speech circuit 20 connected to a line terminal through a (diode) bridge circuit 2 and a switch 1. This photo coupler 3 has an output terminal for connection to a subscriber device to which power is not supplied from the telephone line. This subscriber circuit realizes coupling between the telephone line and the subscriber device while keeping galvanic isolation.

公开(公告)号：JPH07169885A

公开(公告)日：1995-07-04

申请号：JP26730294

申请日：1994-10-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CELLAI MARINO ,  MAGNI PIERANGELO

IPC: H01L23/34 ,  H01L21/56 ,  H01L23/433

Abstract: PURPOSE: To provide an improved chip package which can have improved reliability and extended effective life-time and also can have structural and functional characteristics which is superior than those of a known prior art which have bent proposed thus far. CONSTITUTION: In a chip package, a thermally dissipating device is arranged separately to the both sides of a circuit chip 3 and a support frame 4. In a preferred embodiment, the thermally dissipating device has at least two thermally dissipating elements 15 and 16, which are structurally independent from each other and make contact with each other. The two thermally dissipating elements 15 and 16 are arranged on the support frame 4, symmetrically with respect to the left and right the frame 4.

公开(公告)号：JPH07154833A

公开(公告)日：1995-06-16

申请号：JP17690894

申请日：1994-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： SAVIOTTI VANNI

IPC: H04Q3/42 ,  H04M19/00

Abstract: PURPOSE: To conquer conventional defects by softly inverting the polarity of a telephone line. CONSTITUTION: The system is provided with an output stage 20 connected to a telephone subscriber's line, a line current sensor 30 related to the output stage 20, a voltage/current converter 13, a comparator 12 connected between the output stage 20 and the converter 13, a logic circuit 15 connected to the comparator 12, and plural switches 9, 18, 19, 23, 24.

公开(公告)号：JPH07142974A

公开(公告)日：1995-06-02

申请号：JP11597294

申请日：1994-05-02

Applicant: ST MICROELECTRONICS SRL

Inventor： ROSSI GIORGIO ,  COCETTA FRANCO ,  MARCHIO FABIO

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/58 ,  H03K17/082 ,  H03K17/14 ,  H03K17/16 ,  H03K17/687

Abstract: PURPOSE: To make the operation and a threshold voltage of the circuit independent of temperature substantially so as to keep independency of temperature. CONSTITUTION: The circuit is configured with a transistor(TR) 102 connected in series with an inductive load 101 between 1st and 2nd terminals of a voltage application source and having a control terminal to be connected to a drive circuit 103 and with a control circuit 112 connected between the inductive load 101 and the control terminal. The control circuit 112 is made up of a voltage divider 111 connected between the inductive load 101 and the 1st terminal of the voltage supply source, and a comparator 106 having 1st and 2nd input terminals connected between the voltage divider 111 and a point of a reference voltage (VREF) and an output terminal connecting to the control terminal of the TR 102.

公开(公告)号：JPH07141184A

公开(公告)日：1995-06-02

申请号：JP12784094

申请日：1994-06-09

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： RUSSO BIAGIO ,  POLUZZI RINALDO ,  LUZZI CLAUDIO

IPC: G06F9/44 ,  G05B13/02 ,  G06F1/035 ,  G06N7/02 ,  G06N7/04

Abstract: PURPOSE: To perform an operation at a high calculation speed and at the high degree of a resolution while making a required storage capacity for a hardware to carry out a belonging relation function extremely small. CONSTITUTION: This electronic controller 1A is provided with a buffer part 8 for reproducing the effective value of the belonging relation function and extracting prescribed weight included in the inference rule of fuzzy logic calculation between a storage part 5A for storing a plurality of values of the belonging relation function and the calculation part 6. The storage part 5A is a size corresponding to a large number of non-zero values of the belonging relation function related to a selected point among the finite number of points and the selected point is provided with the maximum number of the non-zero value.

公开(公告)号：JPH07135517A

公开(公告)日：1995-05-23

申请号：JP9365294

申请日：1994-04-06

Applicant: ST MICROELECTRONICS SRL

Inventor： CASSIS MARCO ,  PEDRAZZINI GIORGIO

IPC: H04L29/06 ,  G06F13/40

Abstract: PURPOSE: To provide the interface circuit that is operated in compliance with any selected protocol in two kinds of protocols in response to the needs of a device that is able to be operated in both the protocols because two kinds of protocols have been used for transmission of a control signal to a control circuit conventionally, conventional devices are manufactured according to any of the protocols and this has made the burden for manufacturers. CONSTITUTION: In the case of the 1st standard (SPI), a 3rd signal (CE) fed to a pin (ADDR) is fed to a multiplexer (MUX) as it is, and in the case of the 2nd standard, the 3rd signal (CE) is fed to the multiplexer as a virtual CE signal via a decoder and a recognition signal generating means.

公开(公告)号：JPH07106275A

公开(公告)日：1995-04-21

申请号：JP18026393

申请日：1993-07-21

Applicant: ST MICROELECTRONICS SRL

Inventor： ZACCHERINI CHIARA

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/8244 ,  H01L27/11

Abstract: PURPOSE: To form an implantation region with a low risk for causing a channel phenomenon by implanting a first dopant species with a large atomic weight, making amorphous the polycrystalline silicon at a non-mask part, eliminating the mask, and implanting a second dopant species into the entire region on a semiconductor. CONSTITUTION: An ion is implanted into a specific region 8 of a polycrystalline silicon layer 7 on a field oxide 5. Then, the ion is implanted heavily using an N-type dopant seed 11 with a large atomic weight such as arsenic or phosphorus. When such a heavy implantation process is executed, the polycrystalline silicon layer 7 at a part that is located on a channel region 4 of the device 1 and is not protected by a photoresist 10 becomes amorphous. Then, the protection photoresit 10 is eliminated. After that, a P-type dopant such as boron is implanted with a medium or small amount of dosage.