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公开(公告)号：KR1020170030004A
公开(公告)日：2017-03-16
申请号：KR1020150138116
申请日：2015-09-30
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L27/0924 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/0922 , H01L29/0649 , H01L29/161 , H01L29/66818
Abstract: 반도체장치가제공된다. 상기반도체장치는제1 영역및 제2 영역을포함하는기판, 상기제1 영역상에제1 방향으로연장되는제1 핀, 상기제2 영역상에제2 방향으로연장되는제2 핀, 상기제1 핀의측면상에형성되는제1 라이너와, 상기제1 라이너상에형성되는제2 라이너를포함하는제1 듀얼라이너, 상기제2 핀의측면상에형성되는제3 라이너와, 상기제3 라이너상에형성되는제4 라이너를포함하는제2 듀얼라이너, 및상기제2 핀의상부를둘러싸는에피택셜층을포함하되, 상기제1 라이너의두께는상기제3 라이너의두께와다르다.
Abstract translation: 提供了一种半导体器件。 该半导体器件包括：衬底，包括第一区域和第二区域;在第一区域上沿第一方向延伸的第一鳍状物;在第二区域上沿第二方向延伸的第二鳍状物; 第一衬里，其包括形成在所述第一销的一侧上的第一衬里和形成在所述第一衬里上的第二衬里，形成在所述第二鳍状物的一侧上的第三衬里， 第二双衬里包括形成在衬里上的第四衬里和围绕第二鳍的外延层，其中第一衬里的厚度不同于第三衬里的厚度。
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公开(公告)号：KR1020170022817A
公开(公告)日：2017-03-02
申请号：KR1020150139743
申请日：2015-10-05
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L29/423
CPC classification number: H01L21/76224 , H01L21/31144 , H01L21/823821 , H01L21/823878 , H01L27/0924
Abstract: 반도체장치및 그제조방법이제공된다. 반도체장치의제조방법은기판으로부터돌출된제1 액티브패턴및 제2 액티브패턴을상기기판의제1 영역및 제2 영역에각각형성하고, 상기제2 영역의상기기판및 상기제2 액티브패턴상에제2 극성을갖는제2 라이너패턴을형성하고, 상기제1 영역의상기기판및 상기제1 액티브패턴상에상기제2 극성과다른제1 극성을갖는제1 라이너패턴을형성하고, 상기제1 영역및 상기제2 영역의상기제1 라이너패턴및 상기제2 라이너패턴상에소자분리패턴을형성하고, 상기소자분리패턴을리세스하여상기제1 액티브패턴및 상기제2 액티브패턴을노출시키는것을포함한다.
Abstract translation: 一种用于制造半导体器件的方法包括在衬底的第一区域中形成第一有源图案和在衬底的第二区域中形成第二有源图案，其中第一和第二有源图案从衬底突出，形成第二衬垫图案 在所述基板上和所述第二区域中的所述第二有源图案，其中所述第二衬垫图案具有第二极性，在所述基板上形成第一衬垫图案和所述第一区域中的所述第一有源图案，其中所述第一衬垫图案具有第一极性 与第二极性不同，在第一区域中的第一衬垫图案和第二区域中的第二衬垫图案上形成隔离图案，并且通过凹陷隔离图案来暴露第一活动图案和第二活动图案。
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公开(公告)号：KR1020090076743A
公开(公告)日：2009-07-13
申请号：KR1020080030784
申请日：2008-04-02
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L21/0337 , G03F7/168 , G03F7/38 , G03F7/70466 , H01L21/0338
Abstract: A fine pattern forming method of the semiconductor device is provided, which can obtain the thin film with a superior gap fill property. The first film is formed on the substrate(100). A plurality of first carbon containing film patterns are formed on the first film. The buffer layer covering the upper side and side wall of a plurality of first carbon containing film patterns is formed. The second carbon-containing film pattern is molded on the buffer layer. The buffer layer between the first carbon containing film pattern and the second carbon containing film pattern is removed. The first film is etched and a plurality of first layer patterns are formed.
Abstract translation: 提供一种半导体器件的精细图案形成方法，其可以获得具有优异间隙填充性能的薄膜。 第一膜形成在基板（100）上。 在第一膜上形成多个第一含碳膜。 形成覆盖多个第一含碳膜图案的上侧和侧壁的缓冲层。 第二含碳膜图案被模制在缓冲层上。 除去第一含碳膜图案和第二含碳膜图案之间的缓冲层。 蚀刻第一膜并形成多个第一层图案。
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公开(公告)号：KR1020070095121A
公开(公告)日：2007-09-28
申请号：KR1020060025409
申请日：2006-03-20
Applicant: 삼성전자주식회사
IPC: H01L21/8247
CPC classification number: H01L21/76224 , Y10S438/954
Abstract: A method for manufacturing a non-volatile semiconductor memory device is provided to minimize generation of seams and voids in a floating gate by preventing formation of an undercut region in a floating gate forming region. A pad oxide layer pattern(111) and a mask pattern(113) are formed on a semiconductor substrate(100), and the substrate is etched by using the mask pattern as an etch mask to form a trench. A first isolation film(121) and a second isolation film(123) are formed to bury the trench. The mask pattern is removed to expose an upper surface of the pad oxide layer pattern and sidewalls of the second isolation film. The pad oxide layer pattern and a sidewall of the second device isolation layer exposed by the opening are removed to form a floating gate forming region.
Abstract translation: 提供一种用于制造非易失性半导体存储器件的方法，以通过防止在浮动栅极形成区域中形成底切区域来最小化浮动栅极中的接缝和空隙的产生。 在半导体衬底（100）上形成焊盘氧化物层图案（111）和掩模图案（113），并且通过使用掩模图案作为蚀刻掩模来蚀刻衬底以形成沟槽。 形成第一隔离膜（121）和第二隔离膜（123）以埋置沟槽。 去除掩模图案以暴露焊盘氧化物层图案的上表面和第二隔离膜的侧壁。 去除衬垫氧化物层图案和由开口暴露的第二器件隔离层的侧壁以形成浮栅形成区域。
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公开(公告)号：KR100663357B1
公开(公告)日：2007-01-02
申请号：KR1020050014714
申请日：2005-02-22
Applicant: 삼성전자주식회사
IPC: H01L21/335
CPC classification number: H01L21/32134 , C09K13/02 , H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
Abstract: 금속 질화막 패턴을 갖는 트랜지스터의 형성방법들을 제공한다. 이 방법들은 금속 질화막 패턴을 형성하는 동안 그 패턴 아래의 게이트 절연막에 식각 데미지를 최소화시키는 방안을 제시해준다. 이를 위해서, 반도체 기판 상에 게이트 절연막 및 금속 질화막을 차례로 형성한다. 그리고, 상기 금속 질화막 상에 게이트 전극 및 게이트 캐핑막 패턴을 차례로 형성한다. 상기 게이트 캐핑막 패턴 및 상기 게이트 전극을 식각 마스크로 사용해서 금속 질화막 상에 식각 공정을 수행한다. 상기 식각 공정은 웨트 에천트(wet etchant)를 사용해서 수행한다.
트랜지스터, 금속 질화막, 웨트 에천트.-
Patent Agency Ranking
公开(公告)号：KR1020060088380A
公开(公告)日：2006-08-04
申请号：KR1020050009254
申请日：2005-02-01
Applicant: 삼성전자주식회사
CPC classification number: C11D3/042 , C11D3/30 , C11D3/33 , C11D7/08 , C11D7/265 , C11D7/3209 , C11D7/3218 , C11D7/3245 , C11D11/0047 , C11D1/008 , C11D3/02
Abstract: According to an example embodiment of the present invention, the microelectronic cleaning agent may include a fluoride component, an acid component, a chelating agent, a surfactant and water. Example embodiments of the present invention provide a microelectronic cleaning agent which can selectively remove, for example, a high-k dielectric layer. The microelectronic cleaning agent includes from about 0.001 weight % to about 10 weight % of a fluoride component, from about 0.001 weight % to about 30 weight % of an acid component, from about 0.001 weight % to about 20 weight % of a chelating agent, from about 0.001 weight % to about 10 weight % of a surfactant, and water (H 2 O). The water may comprise the remainder of the cleaning agent. According to another embodiment of the present invention, a method of fabricating a semiconductor device using the microelectronic cleaning agent is also provided.
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公开(公告)号：KR1020140099743A
公开(公告)日：2014-08-13
申请号：KR1020130012529
申请日：2013-02-04
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66795 , H01L29/42316 , H01L29/42336 , H01L29/66348
Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating a semiconductor device includes providing a fin which protrudes from a substrate and a plurality of dummy gate patterns formed on the fin in order to intersect with the fin; forming a first recess in the fin on both sides of the dummy gate patterns; forming an oxide layer on the surface of the first recess; and forming a second recess by removing the oxide layer.
Abstract translation: 提供一种制造半导体器件的方法。 制造半导体器件的方法包括提供从衬底突出的翅片和形成在翅片上的多个虚拟栅极图案，以便与鳍片相交; 在所述伪栅极图案的两侧上形成所述翅片中的第一凹部; 在所述第一凹部的表面上形成氧化物层; 并通过去除氧化物层形成第二凹槽。
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公开(公告)号：KR1020140091856A
公开(公告)日：2014-07-23
申请号：KR1020130003823
申请日：2013-01-14
Applicant: 삼성전자주식회사
IPC: G11C11/15 , H01L21/8247 , H01L27/115
CPC classification number: G11C11/161 , G11C11/15 , H01L27/222 , H01L43/08 , H01L43/12
Abstract: An MTJ formulation step includes the steps of: forming a second interlayer insulating film on a source line and a first interlayer insulating film layer; forming a lower electrode contact by selectively etching the first and second interlayer insulating films; and successively laminating a fixed magnetic film, a tunnel barrier film, a flexible magnetic film, a capping film, and a mask layer and alternatively drying and wetting the respective layers through a multi-step etching process. The present invention can completely remove noble metallic polymers with the wet etching process by alternatively drying and wetting the MJT through a multi-step etching process to acquire a magnetic memory device with excellent magnetic and electrical attributes.
Abstract translation: MTJ制备步骤包括以下步骤：在源极线和第一层间绝缘膜层上形成第二层间绝缘膜; 通过选择性地蚀刻第一和第二层间绝缘膜来形成下电极接触; 依次层叠固定磁性膜，隧道阻挡膜，柔性磁性膜，封盖膜和掩模层，并且通过多步骤蚀刻工艺干燥和润湿各个层。 本发明可以通过湿式蚀刻工艺完全去除贵金属聚合物，通过多步骤蚀刻工艺交替地干燥和润湿MJT，以获得具有优异磁性和电学特性的磁存储器件。
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