公开(公告)号：EP1628515B1

公开(公告)日：2007-09-19

申请号：EP05076577.5

申请日：2005-07-11

Applicant: Delphi Technologies, Inc.

Inventor： Chang, Shih-chia ,  Berlin, Carl W. ,  Myers, Bruce A. ,  Fairchild, Ray M. ,  Peugh, Darrel E.

IPC: H05K7/20 ,  H05K1/02

CPC classification number: H05K7/20254 ,  H05K1/0206 ,  H05K1/0272 ,  H05K3/4611 ,  H05K2201/064

公开(公告)号：EP1798766A2

公开(公告)日：2007-06-20

申请号：EP06077173.0

申请日：2006-12-05

Applicant: Delphi Technologies, Inc.

Inventor： Djordjevic, Aleksandra ,  Berlin, Carl W.

IPC: H01L23/495

CPC classification number: H01L23/49861 ,  H01L21/4846 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method for forming a leadframe assembly (22) is provided. The method includes the steps of providing a sheet (10) of leadframe material and depositing a brazing alloy (12) on a first surface of the sheet (10). The method also includes the steps of placing one or more substrates (16) on the first surface of the sheet (10) and in contact the brazing alloy (12), and heating the brazing alloy (12) to bond the substrate (16) to the first surface of the sheet (10).

Abstract translation: 提供了一种用于形成引线框架组件（22）的方法。 该方法包括以下步骤：提供引线框架材料的片材（10）并且在片材（10）的第一表面上沉积钎焊合金（12）。 该方法还包括以下步骤：将一个或多个基底（16）放置在片材（10）的第一表面上并接触钎焊合金（12），并加热钎焊合金（12）以将基底（16） 到片材（10）的第一表面。

公开(公告)号：EP1589795A1

公开(公告)日：2005-10-26

申请号：EP05075795.4

申请日：2005-04-06

Applicant: Delphi Technologies, Inc.

Inventor： Sarma, Dwadasi H. ,  Heytens, Rhonda J. ,  Berlin, Carl W. ,  Fairchild, Ray M. ,  Myers, Bruce A. ,  Ward, Daniel K.

IPC: H05K1/03 ,  H05K1/02

CPC classification number: H01L23/15 ,  H01L23/3677 ,  H01L23/3731 ,  H01L23/3735 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19107 ,  H05K1/0206 ,  H05K1/0306 ,  H05K3/0061 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/0209 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A circuit board assembly (30) that makes use of a low-temperature co-fired ceramic (LTCC) substrate (10), and a process for producing the assembly (30). The substrate (10) contains at least first and second regions (32,34) formed by a plurality of first ceramic layers (36) and at least one second ceramic layer (38), respectively, that are superimposed and bonded to each other. Conductor lines (22) are present on at least some of the first ceramic layers (36) so as to be between adjacent pairs of the layers (36). Electrically-conductive vias (16) electrically interconnect the conductor lines (22) on different first ceramic layers (36), and a surface-mount IC device (12) is mounted to the substrate (10). The first ceramic layers (36) are formed of electrically-nonconductive materials, while the one or more second ceramic layers (38) contain thermally-conductive particles dispersed in a matrix of electrically-nonconductive materials, such that the one or more second ceramic layers (38) are more thermally conductive than the first ceramic layers (36).

Abstract translation: 使用低温共烧陶瓷（LTCC）基板（10）的电路板组件（30）和用于制造组件（30）的工艺。 衬底（10）至少包含由多个第一陶瓷层（36）和至少一个第二陶瓷层（38）形成的第一和第二区域（32,34），它们彼此叠加并结合。 导体线（22）存在于至少一些第一陶瓷层（36）上，以便在相邻的层（36）之间。 导电通孔（16）将不同第一陶瓷层（36）上的导体线（22）电互连，并且表面安装IC器件（12）安装到基板（10）。 第一陶瓷层（36）由非导电材料形成，而一个或多个第二陶瓷层（38）包含分散在非导电材料的基体中的导热颗粒，使得一个或多个第二陶瓷层 （38）比第一陶瓷层（36）更加导热。

公开(公告)号：EP1473741A2

公开(公告)日：2004-11-03

申请号：EP04076242.9

申请日：2004-04-26

Applicant: Delphi Technologies, Inc.

Inventor： Berlin, Carl W. ,  Morken, James R. ,  Sarma, Dwadasi H. ,  Hart, William ,  Downey, Joel F. ,  McGirr, Kevin J.

IPC: H01C7/00

CPC classification number: H01C17/242 ,  H01C7/003 ,  H01C17/23 ,  Y10T29/49082 ,  Y10T29/49099

Abstract: A thick film current sensing resistor (10) is provided having an input terminal (14) for receiving an electrical current (I), and an output terminal (16) for outputting the electrical current (I). A film of resistive material (20) extends between the input and output terminals (14 and 16) and is electrically coupled to the input and output terminals (14 and 16) so that current (I) flows through the film of resistive material (20). A pair of sensing terminals (24 and 26) are provided to sense a voltage potential (Vs) across the film of resistive material (20). The sensed voltage (Vs) provides an indication of the current (I). An gap (32) is formed in the film of resistive material (20) between the input and output terminals (14 and 16) and the sensing terminals (24 and 26). The length (L A ) of the gap (32) defines a voltage sensing point of the sensing terminals (24 and 26).

Abstract translation: 提供了具有用于接收电流（I）的输入端子（14）和用于输出电流（I）的输出端子（16）的厚膜电流检测电阻器（10）。 电阻材料薄膜（20）在输入和输出端子（14和16）之间延伸并且电耦合到输入和输出端子（14和16），使得电流（I）流过电阻材料膜（20 ）。 提供一对感测端子（24和26）以感测电阻材料膜（20）两端的电压电位（Vs）。 感测电压（Vs）提供电流（I）的指示。 在输入和输出端子（14和16）和感测端子（24和26）之间的电阻材料膜（20）中形成间隙（32）。 间隙（32）的长度（LA）限定了感测端子（24和26）的电压检测点。

公开(公告)号：EP2645839A3

公开(公告)日：2017-04-26

申请号：EP13160107.2

申请日：2013-03-20

Applicant: Delphi Technologies, Inc.

Inventor： Brandenburg, Scott D. ,  Parker, Richard D. ,  Gerbsch, Erich W. ,  Eesley, Gary L. ,  Berlin, Carl W.

IPC: H05K7/20

CPC classification number: H05K7/20927

Abstract: A liquid cooled power electronics assembly (10) configured to use electrically conductive coolant (16) to cool power electronic devices that uses dielectric plates sealed with a metallic seal around the perimeter of the dielectric plates to form a device assembly (10), and then forms another metallic seal between the device assembly (10) and a housing (18). The configuration allows for more direct contact between the electronic device (12) and the coolant (16), while protecting the electronic device (12) from contact with potentially electrically conductive coolant (16). Material used to form the dielectric plates and the housing (18) are selected to have similar coefficients of thermal expansion (CTE) so that the reliability of the seals is maximized.

Abstract translation: 一种液冷功率电子组件（10），其被配置为使用导电冷却剂（16）来冷却功率电子设备，该功率电子设备使用围绕介电板的周边用金属密封件密封的介电板以形成设备组件（10），然后 在装置组件（10）和壳体（18）之间形成另一金属密封。 该配置允许电子设备（12）和冷却剂（16）之间更直接的接触，同时保护电子设备（12）不与潜在导电的冷却剂（16）接触。 选择用于形成电介质板和壳体（18）的材料以具有相似的热膨胀系数（CTE），使得密封件的可靠性最大化。

公开(公告)号：EP2503374A1

公开(公告)日：2012-09-26

申请号：EP12159557.3

申请日：2012-03-15

Applicant: Delphi Technologies, Inc.

Inventor： Kuhlman, Frederick F. ,  Harbach, Andrew P. ,  Berlin, Carl W.

IPC: G02B26/00

CPC classification number: G02B26/005 ,  G09G3/003 ,  G09G2300/023 ,  G09G2340/12 ,  G09G2340/14 ,  G09G2380/10

Abstract: A display for displaying images that includes a transreflective electrowetting layer operable to a transparent-state where light passes through the transreflective electrowetting layer and a reflective-state where light is reflected by the transreflective electrowetting layer; a non-reflective layer underlying the transreflective electrowetting layer; and an emissive layer proximate to the transreflective electrowetting layer. The display combines light emitting elements such as OLED's with transreflective electrowetting elements to provide a display that can operate in high ambient light conditions without undesirably high power dissipation by the OLED's, and can operate under low ambient light or no ambient light conditions.

Abstract translation: 一种用于显示图像的显示器，其包括可操作成透过透反电润湿层的透明状态的反光电润湿层和由反射电润湿层反射光的反射状态; 位于透反电润湿层下面的非反射层; 以及靠近透反电润湿层的发光层。 显示器将诸如OLED的发光元件与透反电润湿元件组合以提供可在高环境光条件下操作的显示器，而不会由OLED产生不期望的高功率耗散，并且可以在低环境光或无环境光条件下操作。

公开(公告)号：EP2079085A2

公开(公告)日：2009-07-15

申请号：EP08172026.0

申请日：2008-12-17

Applicant: Delphi Technologies, Inc.

Inventor： Berlin, Carl W. ,  Zimmerman, David W. ,  Djordjevic, Aleksandra

IPC: H01F17/00 ,  H01F27/34

CPC classification number: H01F17/0013 ,  H01F27/346

Abstract: An inductor (30,130) and method (100) of containing a magnetic field is provided. The inductor (30,130) includes a first set of layers (32,132) wound in a first predetermined direction, wherein each layer of the first set of layers (32,132) is electrically connected to one another, and a second set of layers (34,134) wound in a second predetermined direction, wherein each layer of the second set of layers (34,134) is electrically connected to one another and the first set of layers (32,132), and the second set of layers (34,134) is between a top layer (32A,132A) and a bottom layer (32B,132B), such that the top layer (32A,132A) forms a first pair with a first layer of the second set of layers (34,134), and the bottom layer (32B,132B) forms a second pair with a second layer of the second set of layers (34,134) so that the magnetic field is substantially contained, such as to remain substantially within a gap (35,135) defined between each layer of the pairs of layers.

Abstract translation: 提供了一种包含磁场的电感器（30,130）和方法（100）。 电感器（30,130）包括沿第一预定方向缠绕的第一组层（32,132），其中第一组层（32,132）的每个层彼此电连接，并且第二组层（34,134）缠绕 在第二预定方向上，其中第二组层（34,134）的每个层彼此电连接，并且第一组层（32,132）和第二组层（34,134）位于顶层（32A）之间 ，132A）和底层（32B，132B），使得顶层（32A，132A）与第二组层（34,134）的第一层和底层（32B，132B）形成第一对， 与第二组层（34,134）的第二层形成第二对，使得基本上包含磁场，例如基本上保持在每层层之间限定的间隙（35,135）内。

公开(公告)号：EP2034808A2

公开(公告)日：2009-03-11

申请号：EP08159937.5

申请日：2008-07-08

Applicant: Delphi Technologies, Inc.

Inventor： Djordjevic, Aleksandra ,  Berlin, Carl W.

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/092 ,  H05K1/167 ,  H05K3/1291 ,  H05K2201/0355 ,  H05K2203/1126 ,  H05K2203/171

Abstract: An embedded resistor and capacitor circuit and fabrication method is provided. The circuit includes a substrate, a conductive foil laminated to the substrate, and a thick film dielectric material disposed on the conductive foil. One or more thick film electrodes are formed on the dielectric material and a thick film resistor is formed at least partially contacting the thick film electrodes. A capacitor is formed by an electrode and the conductive foil. The electrodes serve as terminations for the resistor and capacitor.

Abstract translation: 提供了一种嵌入式电阻和电容电路及其制造方法。 电路包括基板，层叠在基板上的导电箔，以及设置在导电箔上的厚膜介电材料。 在电介质材料上形成一个或多个厚膜电极，并且形成至少部分地接触厚膜电极的厚膜电阻器。 电极由电极和导电箔形成。 电极用作电阻和电容器的终端。

公开(公告)号：EP1968363A2

公开(公告)日：2008-09-10

申请号：EP08151813.6

申请日：2008-02-22

Applicant: Delphi Technologies, Inc.

Inventor： Berlin, Carl W. ,  Sarma, Dwadasi H.R. ,  Chappell, William J. ,  Hoppenjans, Eric E.

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0306 ,  H05K1/0313 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09763 ,  Y10T29/435

Abstract: An embedded capacitor method and system is provided for printed circuit boards. The capacitor structure is embedded within an insulator substrate (30B), minimizes real-estate usage, provides a high capacitance, enhances capacitance density, and yet forms an advantageous planar surface topography. A cavity (36) is defined within and contained by an insulator substrate layer (30B), and a dielectric material (38) at least partially fills the cavity (30B). The dielectric material (38) is connected to an electrical conductor (32A, 32B), and vias (34A, 34B) are used for interconnections and traces. In an aspect, a plurality of stacked insulator substrate layers (40B-40F) define a plurality of cavities (41A-41E) filled with the dielectric material (48A-48E), providing even greater capacitance. In another aspect, an array of cavities (76A-76L) is formed in the insulator substrate layer (70). The embedded capacitor can be employed within numerous systems that utilize capacitors including automotive electronics such as a pressure sensor, an engine control module, a transmission controller, and radio systems including satellite radio devices.

Abstract translation: 为印刷电路板提供嵌入式电容器方法和系统。 电容器结构嵌入在绝缘体基板（30B）内，最小化不动产使用，提供高电容，增强电容密度，并形成有利的平面表面形貌。 空腔（36）被限定在绝缘体基底层（30B）内并由绝缘体基底层（30B）容纳，并且至少部分地填充空腔（30B）的电介质材料（38）。 电介质材料（38）连接到电导体（32A，32B），通孔（34A，34B）用于互连和迹线。 在一个方面，多个堆叠的绝缘体衬底层（40B-40F）限定了填充有电介质材料（48A-48E）的多个空腔（41A-41E），从而提供更大的电容。 在另一方面，在绝缘体基底层（70）中形成有空腔阵列（76A-76L）。 嵌入式电容器可以用于利用诸如压力传感器，发动机控制模块，变速器控制器和包括卫星无线电设备的无线电系统在内的汽车电子产品的电容器的众多系统中。

公开(公告)号：EP1837945A1

公开(公告)日：2007-09-26

申请号：EP07075186.2

申请日：2007-03-13

Applicant: Delphi Technologies, Inc.

Inventor： Berlin, Carl W. ,  Nair, Deepukumar M. ,  Walsh, Matthew R.

IPC: H01P1/203

CPC classification number: H01P1/203 ,  H01P1/2005 ,  H05K1/0233 ,  H05K1/0236 ,  H05K3/4069 ,  H05K2201/0215 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2203/0557 ,  H05K2203/104 ,  H05K2203/171

Abstract: Tuned Electromagnetic Bandgap (EBG)devices (10, 30), and a method for making and tuning tuned EBG devices (10, 30) are provided. The method includes the steps of providing first and second overlapping substrates (32, 32a), placing magnetically alignable conductive material (36) between the substrates (32, 32a), and applying a magnetic field (44, 45) in the vicinity of the magnetically alignable conductive material (36) to align at least some of the material into conductive vias (46, 47). The method further includes the steps of physically altering via characteristics of EBG devices (10, 30) to tune the bandpass and resonant frequencies of the EBG devices (10, 30).

Abstract translation: 提供调谐电磁带隙（EBG）装置（10，30），以及用于制备和调谐调谐EBG装置（10，30）的方法。 该方法包括提供第一和第二重叠衬底（32，32A）的步骤，放置磁性对准基板之间能够导电材料（36）（32，32A），和施加磁场（44,45）中的附近 磁性对准能够导电材料（36）以对齐的至少一些的材料的成导电通孔（46，47）。 该方法包括经由EBG设备的特性的进一步的物理改变的步骤（10，30）来调谐带通和EBG装置的共振频率（10，30）。