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公开(公告)号：GB2566664A
公开(公告)日：2019-03-20
申请号：GB201901265
申请日：2017-06-13
Applicant: IBM
Inventor： HARIKLIA DELIGIANNI , EUGENE O'SULLIVAN , NAIGANG WANG , BRUCE DORIS
IPC: H01F17/00 , H01L23/522
Abstract: A magnetic laminating structure includes alternating layers of a magnetic material (112) and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer (114A) abutting at least on additional insulating layer (114B), and wherein the first insulating layer (114A) and the at least one additional insulating layer (114B) comprise different dielectric materials and/or are formed by a different deposition process.
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公开(公告)号：GB2600899B
公开(公告)日：2022-11-02
申请号：GB202202503
申请日：2020-07-31
Applicant: IBM
Inventor： POUYA HASHEMI , BRUCE DORIS , EUGENE O'SULLIVAN , MICHAEL F LOFARO
Abstract: A memory structure is provided that avoids high resistance due to the galvanic effect. The high resistance is reduced and/or eliminated by providing a T-shaped bottom electrode structure of uniform construction (i.e., a single piece). The T-shaped bottom electrode structure includes a narrow base portion and a wider shelf portion. The shelf portion of the T-shaped bottom electrode structure has a planar topmost surface in which a MTJ pillar forms an interface with.
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公开(公告)号：GB2575748B
公开(公告)日：2022-07-13
申请号：GB201915102
申请日：2018-03-20
Applicant: IBM
Inventor： SUFI ZAFAR , EUGENE O'SULLIVAN , BRUCE DORIS
IPC: G01N27/403 , A61B5/053 , C12Q1/6837
Abstract: Embodiments of the invention include a method of using a sensor. The method includes accessing a sample and exposing the sample to the sensor. The sensor includes a sensing circuit having with a field effect transistor (FET) having a gate structure. A cavity is formed in a fill material that is over the gate structure. A probe of the sensor is within a portion of the cavity. An upper region of the probe is above a top surface of the fill material, and a lower region of the probe is below the top surface of the fill material. The probe structure includes a 3D sensing surface structure, and a liner is formed on the 3D sensing surface and configured to function as a recognition element. A portion of the liner is on the lower region of the probe and positioned between sidewalls of the cavity and the 3D sensing surface.
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公开(公告)号：GB2600899A
公开(公告)日：2022-05-11
申请号：GB202202503
申请日：2020-07-31
Applicant: IBM
Inventor： POUYA HASHEMI , BRUCE DORIS , EUGENE O'SULLIVAN , MICHAEL F LOFARO
Abstract: A memory structure is provided that avoids high resistance due to the galvanic effect. The high resistance is reduced and/or eliminated by providing a T-shaped bottom electrode structure of uniform construction (i.e., a single piece). The T-shaped bottom electrode structure includes a narrow base portion and a wider shelf portion. The shelf portion of the T-shaped bottom electrode structure has a planar topmost surface in which a MTJ pillar forms an interface with.
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公开(公告)号：GB2594868A
公开(公告)日：2021-11-10
申请号：GB202110417
申请日：2019-12-17
Applicant: IBM
Inventor： NATHAN MARCHACK , BRUCE DORIS , POUYA HASHEMI
IPC: H01L21/00
Abstract: A bottom electrode structure for MRAM or MTJ-based memory cells comprises a taper so that the bottom CD is smaller than the top CD. A process of making a bottom electrode contact structure comprises etching a dielectric layer using a plasma chemistry with an increased degree of polymerization. We obtain a product made by this process.
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Patent Agency Ranking
公开(公告)号：GB2550740B
公开(公告)日：2020-05-20
申请号：GB201712260
申请日：2016-01-04
Applicant: IBM
Inventor： BRUCE DORIS , KERN RIM , ALEXANDER REZNICEK , DARSEN DUANE LU , ALI KHAKIFIROOZ , KANGGUO CHENG
IPC: H01L21/84 , H01L27/12 , H01L29/423 , H01L29/66
Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.
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公开(公告)号：GB2602738A
公开(公告)日：2022-07-13
申请号：GB202203398
申请日：2020-08-18
Applicant: IBM
Inventor： BRUCE DORIS , THITIMA SUWANNASIRI , NATHAN MARCHACK , POUYA HASHEMI
Abstract: A multilayered bottom electrode for a magnetic tunnel junction (MTJ) containing device is provided that includes, from bottom to top, a base segment having a first diameter and composed of a remaining portion of a first bottom electrode metal-containing layer, a middle segment having a second diameter and composed of a remaining portion of a second bottom electrode metal-containing layer, and an upper segment having a third diameter and composed of a remaining portion of a third bottom electrode metal-containing layer, wherein the first diameter is greater than the second diameter, and the third diameter is equal to, or less than, the second diameter. The wider base segment of each multilayered bottom electrode prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.
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公开(公告)号：GB2566664B
公开(公告)日：2020-03-11
申请号：GB201901265
申请日：2017-06-13
Applicant: IBM
Inventor： HARIKLIA DELIGIANNI , EUGENE O'SULLIVAN , NAIGANG WANG , BRUCE DORIS
IPC: H01F17/00 , H01L23/522
Abstract: A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer abutting at least one additional insulating layer, wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials and/or are formed by a different deposition process, and wherein the layers of the magnetic material have a cumulative thickness greater than 1 micron.
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公开(公告)号：GB2556224B
公开(公告)日：2019-10-30
申请号：GB201720310
申请日：2016-05-06
Applicant: IBM
Inventor： SIVANANDA KANAKASABAPATHY , FEE LI LIE , GAURI KARVE , SOON-CHEON SEO , STUART SIEG , HONG HE , DERRICK LIU , BRUCE DORIS
IPC: H01L21/336 , H01L29/78
Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.
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公开(公告)号：GB2556260B
公开(公告)日：2019-09-25
申请号：GB201801219
申请日：2016-12-15
Applicant: IBM
Inventor： RAJASEKHAR VENIGALLA , SEONG-DONG KIM , BRUCE DORIS , BRENT A ANDERSON
IPC: H01L27/092 , H01L21/8238
Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.
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