11.
    发明专利
    未知

    公开(公告)号:DE19651029C2

    公开(公告)日:1999-12-02

    申请号:DE19651029

    申请日:1996-12-09

    Applicant: IBM

    Abstract: The invention relates to calibration standards which are used chiefly for the calibration of profilometers and in atomic force- and scanning probe microscopes. The calibration standard has one step of defined height H or a multi-step system formed of several steps of the same step-height H and consisting of exactly one material. The manufacturing procedure for the calibration standard requires only a single masking layer for each of the different versions in the form of a one-step standard or a multi-step system.

    13.
    发明专利
    未知

    公开(公告)号:FR2740224A1

    公开(公告)日:1997-04-25

    申请号:FR9612844

    申请日:1996-10-15

    Applicant: IBM

    Abstract: The invention relates to a contact probe arrangement for electrically connecting a test system with contact pads of a device to be tested. The contact probes are located in guide grooves. The guide grooves as well as areas are provided in a plane parallel to the surface of a guide plate and are covered by a protective plate. The contact probes may bend out laterally into the respective areas. This assures a very dense contact probe array. Contact probe arrays of this type may be used, for example, for detecting opens and shorts in integrated circuits or semiconductor chips. The invention overcomes the problem of adjusting for height differences in the contact pads caused by an uneven surface of the device to be tested.

    High availability, high precision system clock register arrangement

    公开(公告)号:GB2489307A

    公开(公告)日:2012-09-26

    申请号:GB201204158

    申请日:2012-03-09

    Applicant: IBM

    Abstract: A time of day (TOD) system clock associated with a processing core (2) comprises a host clock register (5) incremented by means of a high precision oscillator (3) and a firmware clock register (6), incremented every time the host clock register (5) is incremented. The system monitors for failures of the host clock register (5), and during a failure of the host clock register (5) increments the firmware clock register (6) by means of timing signals of the processing core (2). Upon receiving a clock value read request providing the content of the host clock register (5) if no failure is detected and updating the firmware clock register (6) with the value of the host clock register (5).

    16.
    发明专利
    未知

    公开(公告)号:FR2740224B1

    公开(公告)日:1998-12-31

    申请号:FR9612844

    申请日:1996-10-15

    Applicant: IBM

    Abstract: The invention relates to a contact probe arrangement for electrically connecting a test system with contact pads of a device to be tested. The contact probes are located in guide grooves. The guide grooves as well as areas are provided in a plane parallel to the surface of a guide plate and are covered by a protective plate. The contact probes may bend out laterally into the respective areas. This assures a very dense contact probe array. Contact probe arrays of this type may be used, for example, for detecting opens and shorts in integrated circuits or semiconductor chips. The invention overcomes the problem of adjusting for height differences in the contact pads caused by an uneven surface of the device to be tested.

    Mask production from membrane-covered single crystal silicon@

    公开(公告)号:DE19710798C1

    公开(公告)日:1998-07-30

    申请号:DE19710798

    申请日:1997-03-17

    Applicant: IBM

    Abstract: In the production of a mask with mask areas and thin support walls (1) which are covered with a membrane (2) and which are formed by anisotropic plasma etching of a single crystal silicon body, a wet etching step is carried out just before reaching the membrane (2) and the support walls (1) are aligned parallel to the 100 direction of the silicon body. Preferably, wet etching is carried out with an alkaline solution and the membrane is a 0.2-2 mu thick membrane of heavily doped silicon, silicon nitride or a SiO2/Si3N4/SiO2 layer combination which is covered on both sides with either a heavy metal-coated silicon nitride layer or a heavy metal layer.

    19.
    发明专利
    未知

    公开(公告)号:DE59800259D1

    公开(公告)日:2000-10-12

    申请号:DE59800259

    申请日:1998-01-28

    Applicant: IBM

    Abstract: In an electron or particle beam structuring mask, consisting of a semiconductor wafer (2) with an apertured layer (1) on one surface and with a recess (3) extending from the other surface to the layer-bearing surface, the layer (1) is a preferably 0.1-2.0 mu m thick silicon nitride layer. Also claimed is a similar electron beam structuring mask having, between the apertured layer (31) and the wafer (32), a continuous layer (30) consisting of a combination of silicon dioxide (34), silicon nitride (35) and silicon dioxide (36) layers of relative thicknesses such that the combination is under a slight tensile stress preferably of about 10 dynes/cm . Also claimed is a mask production process involving plasma etching of the apertures in the mask-defining layer (1, 31) at -90 to -140 degrees C using a helicon source for plasma generation and an etching gas mixture of SF6 and O2 in a ratio resulting in perpendicular aperture walls.

    Field emission component for array of emissive flat display screen

    公开(公告)号:DE19800555A1

    公开(公告)日:1999-07-15

    申请号:DE19800555

    申请日:1998-01-09

    Applicant: IBM

    Abstract: A field emission component has several electron emission tips (2) arranged in each of several circular gate holes (5) formed through electrodes. An Independent claim is also included for the production of a field emission component by coating a single crystal silicon substrate with an insulating layer (3), applying a gate metal layer (4) and a photoresist layer on the insulating layer, forming a hole pattern in the resist layer by photolithography, transferring and opening the hole pattern into the gate metal layer by etching, producing tips (2) in the substrate in the hole regions by plasma etching and then applying a back face metallization onto the substrate.

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