公开(公告)号：EP2404316A4

公开(公告)日：2016-04-06

申请号：EP10770142

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

公开(公告)号：EP1905074A4

公开(公告)日：2012-06-27

申请号：EP06773946

申请日：2006-06-26

Applicant: IBM

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  WILLIAMS RICHARD Q

IPC: H01L21/84 ,  H01L27/108 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0811 ,  H01L28/40 ,  H01L29/78648 ,  Y10T436/235 ,  Y10T436/25125 ,  Y10T436/2525 ,  Y10T436/25375

公开(公告)号：EP1792346A4

公开(公告)日：2009-09-09

申请号：EP05805693

申请日：2005-09-19

Applicant: IBM

Inventor： ANDERSON BRENT A ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L29/737 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/739 ,  H01L29/76

CPC classification number: H01L29/0653 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.

公开(公告)号：EP1779436A4

公开(公告)日：2009-05-13

申请号：EP05790060

申请日：2005-06-20

Applicant: IBM

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L27/01 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

公开(公告)号：EP1586108A4

公开(公告)日：2009-03-04

申请号：EP02798556

申请日：2002-12-19

Applicant: IBM

Inventor： BREITWISCH MATTHEW ,  NOWAK EDWARD J

IPC: H01L27/11 ,  H01L21/00 ,  H01L21/44 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/11 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/66765 ,  H01L29/785

Abstract: An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a first channel region (112) disposed on the first gate region and a source (110) and drain (114) formed on either side of the first channel region. The FinFET transistor (N3) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure (102), having a second channel region (118) and a source (116) and drain (120) formed on either side of the second channel region, and a second gate region (122) comprised of the semiconductor layer, disposed on the second channel region.

公开(公告)号：EP1620891A4

公开(公告)日：2007-03-28

申请号：EP04707026

申请日：2004-01-30

Applicant: IBM

Inventor： RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66795

Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

公开(公告)号：EP2446466A4

公开(公告)日：2012-09-12

申请号：EP10792499

申请日：2010-06-02

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J

IPC: H01L21/84 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L21/28123 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material to expose the temporary spacer gates and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material. The method additionally includes filling the space between the active regions and above the remaining portion of the dielectric material with a gate material.

公开(公告)号：EP2401761A4

公开(公告)日：2012-04-25

申请号：EP10780978

申请日：2010-05-04

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC: H01L21/8244 ,  H01L21/8234 ,  H01L27/11

CPC classification number: H01L27/0207 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104

公开(公告)号：EP2380199A4

公开(公告)日：2012-02-29

申请号：EP09835568

申请日：2009-12-15

Applicant: IBM

Inventor： BOTULA ALAN B ,  NOWAK EDWARD J

IPC: H03K17/693 ,  H01L27/12 ,  H01P1/15

CPC classification number: H01L27/1203 ,  H01L27/0218 ,  H01P1/15 ,  H03K17/693 ,  H03K2217/0018

公开(公告)号：EP1886156A4

公开(公告)日：2010-12-29

申请号：EP06759378

申请日：2006-05-09

Applicant: IBM

Inventor： NOWAK EDWARD J ,  NA MYUNG-HE

IPC: H01L29/00 ,  H01L29/76

CPC classification number: H01L22/34 ,  H01L29/42384 ,  H01L29/78609 ,  H01L29/78615