公开(公告)号：GB2493244A

公开(公告)日：2013-01-30

申请号：GB201210426

申请日：2012-06-13

Applicant: IBM

Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  SADANA DEVENDRA

IPC: H01L31/18

Abstract: A method of controlled layer transfer is provided. The method includes providing a stressor layer 16 to a base substrate. The stressor layer has a stressor layer portion 16A located atop an upper surface (12, fig. 1) of the base substrate 10 and a self-pinning stressor layer portion 16B located adjacent each sidewall edge of the base substrate. A spalling inhibitor (20) is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion by applying a laser or chemical etch to the self-pinning stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion to control the spalling.

公开(公告)号：GB2492444A

公开(公告)日：2013-01-02

申请号：GB201208147

申请日：2012-05-10

Applicant: IBM

Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  CORTES NORMA EDITH SOSA ,  SHAHRJERDI DAVOOD ,  SADANA DEVENDRA

IPC: H01L31/18

Abstract: A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region (14) where the stressor layer (16) is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In a preferred embodiment of the present invention, the method includes forming an edge exclusion material (14) on an upper surface and near an edge of a base substrate (10â â ). A stressor layer (16) is then formed on exposed portions of the upper surface of the base substrate (10â â ) and atop the edge exclusion material (14). A portion (10â ) of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled and separated from the bulk of the substrate. The material is removed from the substrate by stresses caused by the stressor layer. An adhesive layer (15) can be formed between the substrate and stressor layer. This method improves the reusability of the substrate.

公开(公告)号：GB2491930A

公开(公告)日：2012-12-19

申请号：GB201206430

申请日：2012-04-12

Applicant: IBM

Inventor： CHENG CHENG-WEI ,  BEDELL STEPHEN ,  SHIU KUEN-TING ,  SADANA DEVENDRA ,  CORTES NORMA EDITH SOSA

IPC: H01L21/762 ,  H01L31/18

Abstract: A method of removing a semiconductor device layer from a base substrate comprising providing a crack propagation layer 12 on an upper surface of a base substrate 10; a semiconductor device layer 14 including at least one semiconductor device is formed on the crack propagation layer 12; etching the end portions of the crack propagation layer 12 to initiate a crack in the crack propagation layer 12; the etched crack propagation layer 15 is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer 14 and another cleaved crack propagation layer portion to the upper surface of the base substrate 10; the cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer 14 and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate 10. Prior to etching the crack propagation layer 12, a stressor 16 may be applied to the device layer; the stressor 16 may further be bonded to a polymer support 18. The present method allows for cleaving of a semiconductor device layer 14 from a substrate 10 at a controlled location.

公开(公告)号：GB2490606A

公开(公告)日：2012-11-07

申请号：GB201208994

申请日：2011-02-16

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  LAURO PAUL A ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD

IPC: H01L21/02 ,  H01L31/18

Abstract: A method for spalling a layer from an ingot of a semiconductor substrate includes forming a metal layer on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot; and removing the layer from the ingot at the fracture. A system for spalling a layer from an ingot of a semiconductor substrate includes a metal layer formed on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot, and wherein the layer is configured to be removed from the ingot at the fracture.

公开(公告)号：GB2489830A

公开(公告)日：2012-10-10

申请号：GB201206801

申请日：2011-02-01

Applicant: IBM

Inventor： BEDELL STEPHEN ,  KIM JEE HWAN ,  INNS DANIEL ,  SADANA DEVENDRA ,  FOGEL KEITH ,  VICHICONTI JAMES

IPC: H01L21/18 ,  H01L21/02 ,  H01L21/30

Abstract: A method for layer transfer using a boron-doped silicon germanium (SiGe) layer includes forming a boron-doped SiGe layer on a bulk silicon substrate; forming an upper silicon (Si) layer over the boron-doped SiGe layer; hydrogenating the boron-doped SiGe layer; bonding the upper Si layer to an alternate substrate; and propagating a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate. A system for layer transfer using a boron-doped silicon germanium (SiGe) layer includes a bulk silicon substrate; a boron-doped Si Ge layer formed on the bulk silicon substrate, such that the boron-doped SiGe layer is located underneath an upper silicon (Si) layer, wherein the boron- doped SiGe layer is configured to propagate a fracture at an interface between the boron- doped SiGe layer and the bulk silicon substrate after hydrogenation of the boron-doped SiGe layer; and an alternate substrate bonded to the upper Si layer.

公开(公告)号：AU2021211858A1

公开(公告)日：2022-06-09

申请号：AU2021211858

申请日：2021-01-15

Applicant: IBM

Inventor： HOLMES STEVEN ,  SADANA DEVENDRA ,  WACASER BRENT ,  FARMER DAMON

IPC: H01L39/02 ,  H01L39/24

Abstract: Techniques regarding qubit devices comprising silicon-based Josephson junctions and/or the manufacturing of qubit devices comprising silicon-based Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a Josephson junction comprising a tunnel barrier positioned between two vertically stacked superconducting silicon electrodes.

公开(公告)号：AU2020384653A1

公开(公告)日：2022-04-21

申请号：AU2020384653

申请日：2020-11-10

Applicant: IBM

Inventor： HOLMES STEVEN ,  BEDELL STEPHEN ,  HART SEAN ,  SADANA DEVENDRA ,  LI NING ,  GUMANN PATRYK

IPC: H01L27/18 ,  B82Y10/00 ,  G06N10/00 ,  H01L39/22 ,  H01L39/24

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer (410), a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of a first surface of an underlying semiconductor layer (340) outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. The sensing region and a portion of the device of the superconductor layer are exposed. A sensing region contact (202) is formed by coupling the first surface of the semiconductor layer with a first metal layer. A nanorod contact (206, 212) using the first metal within the portion of the device region outside the sensing region is formed. By depositing a second metal layer on a second surface of the semiconductor layer within the sensing region, a tunnel junction gate (204) is formed.

公开(公告)号：DE112019002427T5

公开(公告)日：2021-02-11

申请号：DE112019002427

申请日：2019-06-18

Applicant: IBM

Inventor： DE SOUZA JOEL PEREIRA ,  COLLINS JOHN ,  SADANA DEVENDRA ,  BEDELL STEPHEN ,  OTT JOHN ,  HOPSTAKEN MARINUS JOHANNES PETRUS

IPC: H01M10/052 ,  H01M4/134 ,  H01M4/1395 ,  H01M10/056

Abstract: Es werden wiederaufladbare Lithium-Ionen-Batterien bereitgestellt, welche eine hohe Kapazität aufweisen. Die Lithium-Ionen-Batterien enthalten eine Anodenstruktur, die von einheitlicher Konstruktion ist und eine nicht-poröse Zone und eine poröse Zone aufweist, welche eine obere poröse Schicht (Poröse Zone 1) mit einer ersten Dicke und einer ersten Porosität und eine untere poröse Schicht (Poröse Zone 2) umfasst, die unterhalb der oberen porösen Schicht angeordnet ist und eine Grenzfläche mit der nicht-porösen Zone bildet. Zumindest ein oberer Abschnitt der nicht-porösen Zone und die Gesamtheit der porösen Zone sind aus Silicium aufgebaut und die untere poröse Schicht weist eine zweite Dicke auf, die größer als die erste Dicke ist, und weist eine zweite Porosität auf, die größer als die erste Porosität ist.

公开(公告)号：DE112018005625B4

公开(公告)日：2021-02-11

申请号：DE112018005625

申请日：2018-11-16

Applicant: IBM

Inventor： LI NING ,  LEE YUN SEOG ,  DE SOUZA JOEL ,  SADANA DEVENDRA

IPC: H01L27/04 ,  H01L21/8258 ,  H01L27/24 ,  H01L29/49

Abstract: Halbleiterstruktur, aufweisend:ein Halbleitersubstrat (10), welches mindestens eine Kanalzone (11) umfasst, die zwischen Source/Drain-Zonen (12L, 12R) positioniert ist;ein Gate-Dielektrikumsmaterial (14), welches auf der Kanalzone des Halbleitersubstrats angeordnet ist; undeinen Batteriestapel (16), welcher auf dem Gate-Dielektrikumsmaterial angeordnet ist, wobei der Batteriestapel einen Kathodenstromkollektor (18), der auf dem Gate-Dielektrikumsmaterial angeordnet ist, ein Kathodenmaterial (20), das auf dem Kathodenstromkollektor angeordnet ist, ein erstes lonendiffusionsbarrieren-Material (22), das auf dem Kathodenmaterial angeordnet ist, einen Elektrolyten (24), der auf dem ersten lonendiffusionsbarrieren-Material angeordnet ist, ein zweites lonendiffusionsbarrieren-Material (26), das auf dem Elektrolyten angeordnet ist, eine Anodenzone (28), die auf dem zweiten lonendiffusionsbarrieren-Material angeordnet ist, und einen Anodenstromkollektor (30) aufweist, der auf der Anodenzone angeordnet ist,wobei die Anodenzone (28) eine Anhäufungszone ist, die sich während eines Lade /Wiederaufladeverfahrens bildet.

公开(公告)号：GB2492444B

公开(公告)日：2013-08-14

申请号：GB201208147

申请日：2012-05-10

Applicant: IBM

Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  CORTES NORMA EDITH SOSA ,  SHAHRJERDI DAVOOD ,  SADANA DEVENDRA

IPC: H01L31/18