公开(公告)号：MY136302A

公开(公告)日：2008-09-30

申请号：MYPI20021594

申请日：2002-04-30

Applicant: IBM

Inventor： SOLOMON PAUL M ,  SHAW JANE MARGARET ,  KAGAN CHERIE R ,  DIMITRAKOPOULOS CHRISTOS DIMITRIOS ,  NING TAK HUNG

IPC: D02G3/44 ,  H01L29/06 ,  H01L29/786 ,  H01L41/08 ,  H01L41/113 ,  H01L51/00 ,  H01L51/05

Abstract: ACTIVE DEVICES THAT HAVE EITHER A THREAD OR A RIBBON GEOMETRY. THE THREAD GEOMETRY INCLUDES SINGLE THREAD ACTIVE DEVICES (105,170,190) AND MULTIPLE THREAD DEVICES(50,90,100,120,140). SINGLE THREAD DEVICES HAVE A CENTRAL CORE (154,174,194) THAT MAY CONTAIN DIFFERENT MATERIALS DEPENDING UPON WHETHER THE ACTIVE DEVICE IS RESPONSIVE TO ELECTRICAL, LIGHT, MECHANICAL, HEAT, OR CHEMICAL ENERGY. SINGLE THREAD ACTIVE DEVICES INCLUDE FETS, ELECTRO-OPTICAL DEVICES, STRESS TRANSDUCERS, AND THE LIKE. THE ACTIVE DEVICES INCLUDE A SEMICONDUCTOR BODY (158,176,196) THAT FOR THE SINGLE THREAD DEVICES IS A LAYER ABOUT THE CORE OF THE THREAD. FOR THE MULTIPLE THREAD DEVICES, THE SEMICONDUCTOR BODY IS EITHER A LAYER(72,76,78,80) ON ONE OR MORE OF THE THREADS OR AN ELONGATED BODY(110,130) DISPOSED BETWEEN TWO OF THE THREADS. FOR EXAMPLE, A FET IS FORMED OF THREE THREADS, ONE (54,56) OF WHICH CARRIES A GATE INSULATOR LAYER AND A SEMICONDUCTOR LAYER AND THE OTHER TWO (58,60) OF WHICH ARE ELECTRICALLY CONDUCTIVE AND SERVE AS THE SOURCE AND DRAIN. THE SUBSTRATES OR THREADS ARE PREFERABLY FLEXIBLE AND CAN BE FORMED IN A FABRIC.FIGURE 1

公开(公告)号：DE112012002454T5

公开(公告)日：2014-03-27

申请号：DE112012002454

申请日：2012-07-02

Applicant: IBM

Inventor： SOLOMON PAUL M ,  ELMEGREEN BRUCE G ,  MARTYNA GLENN J ,  ROSSNAGEL STEPHEN M ,  NEWNS DENNIS M

IPC: H01L41/00

Abstract: Ein piezoelektronischer Transistor (PET) mit 4 Anschlüssen, welcher ein piezoelektrisches (PE) Material, das zwischen einer ersten und zweiten Elektrode angeordnet ist; ein Isolatormaterial, das auf der zweiten Elektrode angeordnet ist; eine dritte Elektrode, die auf dem Isolatormaterial angeordnet ist und ein piezoresistives (PR) Material umfasst, das zwischen der dritten Elektrode und einer vierten Elektrode angeordnet ist. Eine über die erste und zweite Elektrode angelegte Spannung bewirkt, dass ein Druck von dem PE Material durch das Isolatormaterial auf das PR Material ausgeübt wird, wobei der elektrische Widerstand des PR Materials von dem Druck abhängt, der von dem PE Material ausgeübt wird. Die erste und zweite Elektrode sind von der dritten und vierten Elektrode elektrisch isoliert. Ebenfalls offenbart werden Logikeinheiten, die aus PETs mit 4 Anschlüssen hergestellt werden, und ein Verfahren zur Herstellung eines PET mit 4 Anschlüssen.

公开(公告)号：GB2485493B

公开(公告)日：2014-01-15

申请号：GB201200163

申请日：2010-08-04

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  EDELSTEIN DANIEL C ,  KIM HO-CHEOL ,  KOESTER STEVEN ,  SOLOMON PAUL M ,  HINSBERG WILLIAM

IPC: H01L21/44 ,  H01L21/311 ,  H01L21/768

Abstract: An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different.

公开(公告)号：GB2485495B

公开(公告)日：2013-10-30

申请号：GB201200880

申请日：2010-08-30

Applicant: IBM

Inventor： BJOERK MIKAEL T ,  KARG SIEGFRIED FRIEDRICH ,  KNOCH JOACHIM ,  RIEL HEIKE E ,  RIESS WALTER H ,  SOLOMON PAUL M

IPC: H01L29/739 ,  H01L29/06

Abstract: An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state.

公开(公告)号：DE112010003495T5

公开(公告)日：2012-09-20

申请号：DE112010003495

申请日：2010-08-30

Applicant: IBM

Inventor： KARG SIEGFRIED ,  BJOERK MIKAEL T ,  KNOCH JOACHIM ,  RIEL HEIKE ,  RIESS WALTER H ,  SOLOMON PAUL M

IPC: H01L29/739 ,  H01L29/06

Abstract: Ein indirekt induzierter Tunnelemitter für eine Tunnelfeldeffekttransistor(TFET)-Struktur umfasst einen äußeren Mantel, der zumindest teilweise ein längliches Kernelement umgibt, wobei das längliche Kernelement aus einem ersten Halbleitermaterial gebildet ist; eine Isolatorschicht, die zwischen dem äußeren Mantel und dem Kernelement angeordnet ist; wobei der äußere Mantel an einer Stelle angeordnet ist, die einer Source-Zone der TFET-Struktur entspricht; und einen Source-Kontakt, der den äußeren Mantel mit dem Kernelement kurzschließt; wobei der äußere Mantel so aufgebaut ist, dass er in die Source-Zone des Kernelements eine Ladungsträgerkonzentration einführt, die zum Tunneln in eine Kanalzone der TFET-Struktur während eines EIN-Zustands ausreicht.

公开(公告)号：CA1298670C

公开(公告)日：1992-04-07

申请号：CA611437

申请日：1989-09-14

Applicant: IBM

Inventor： SOLOMON PAUL M ,  WRIGHT STEVEN L

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/165 ,  H01L29/778 ,  H01L21/335 ,  H01L29/76

Abstract: YO986-100 GERMANIUM CHANNEL SILICON MOSFET An alloy layer comprising germanium and silicon is grown on top of a silicon substrate. The alloy layer is kept thin enough for proper pseudomorphic, dislocation free growth. A layer of silicon is applied to the alloy layer. The initial silicon layer is from two to three times as thick as the alloy layer. Approximately the upper two-thirds of the silicon layer is oxidized, either thermally, anodically or by plasma anodization. The silicon layer that remains between the silicon dioxide and the alloy layer is kept thin enough so that a parasitic channel does not form on the interface between the silicon and the silicon dioxide. The germanium alloyed channel is thus suitably bounded by silicon crystalline structures on both of the channel layer surfaces. The barrier heights between silicon dioxide and silicon are very large thus providing good carrier confinement. A suitably applied voltage will result in a region of high mobility charge carriers at the interface between the alloy layer and the upper silicon layer.