公开(公告)号：DE102004057536B3

公开(公告)日：2006-05-11

申请号：DE102004057536

申请日：2004-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OFFENBERG DIRK ,  KIESLICH ALBRECHT ,  WEGE STEPHAN

IPC: H01L21/308 ,  H01L21/28

Abstract: A method for fabrication of openings with at least two different structure sizes in one layer (2) by etching by means of an auxiliary layer (4,6). The auxiliary layer (4,6), for generating n different structural sizes is provided with n different layer thicknesses (d1,d2), and in the auxiliary layer (4,6) are made through-holes (8,9) which have at the top surface a first structural size and a second structural size at the lower surface. The layer (2) is etched via the through-holes (8,9) for making the openings (not shown here).

公开(公告)号：DE10356476B3

公开(公告)日：2005-06-30

申请号：DE10356476

申请日：2003-12-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  SCHUSTER THOMAS ,  MUELLER RALF ,  KIESLICH ALBRECHT ,  ALSMEIER JOHANN ,  OFFENBERG DIRK ,  GOLDBACH MATTHIAS

IPC: H01L27/108 ,  H01L21/265 ,  H01L21/8242

Abstract: A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

公开(公告)号：DE10142595C2

公开(公告)日：2003-10-09

申请号：DE10142595

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  KIESLICH ALBRECHT ,  SACHSE HERMANN ,  FELDNER KLAUS

IPC: H01L21/3105 ,  H01L21/762 ,  H01L21/8242

Abstract: A method for planarizing the surface of an isolating layer that is deposited on a semiconductor body is described. Zones where the isolating layer has a low level are covered with a block mask in order to be able to selectively etch zones of the isolating layer with a higher level.

公开(公告)号：DE10141485A1

公开(公告)日：2003-03-13

申请号：DE10141485

申请日：2001-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIESLICH ALBRECHT ,  SACHSE HERMANN

IPC: G03F1/00 ,  G03F1/14

Abstract: A mask for fabricating semiconductor components contains first transparent regions and second transparent regions. The second regions are laid out such that they do not act on the regions of the photoresist directly beneath them in the exposure of the photoresist through the mask. The transparent regions define a size and a shape of structures to be formed.

公开(公告)号：DE19945425A1

公开(公告)日：2001-04-19

申请号：DE19945425

申请日：1999-09-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEIBERG WOLFGANG ,  BAUCH LOTHAR ,  LEHR MATTHIAS UWE ,  LUEKEN ELKE ,  MOLL PETER ,  VOGT MIRKO ,  KIESLICH ALBRECHT

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/321 ,  G03F7/20

Abstract: Structuring a metal layer (M) during semiconductor finishing comprises applying a lacquer layer (L) to a semiconductor substrate; structuring the lacquer layer using lithography and producing an etching mask; and structuring the metal layer using the mask. Initially a hard mask is applied to the metal layer and the lacquer layer is applied to the mask, where the lacquer layer is thin so that only the mask and not the metal layer can be structured with the aid of the lacquer layer. The hard mask is structured to form an etching mask with the aid of the structured lacquer layer. The metal layer is structured with the hard mask as an etching mask. Preferred Features: The hard mask has a first layer (H1) of an oxide, preferably silicon dioxide, and a second layer (H2) to reduce reflection and made of silicon nitride. The metal layer is made of aluminum and/or copper.

公开(公告)号：DE19944304A1

公开(公告)日：2001-04-05

申请号：DE19944304

申请日：1999-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： UWE MATTHIAS ,  KIESLICH ALBRECHT ,  THIEME PETER ,  VOLAND LARS

IPC: H01L21/3105 ,  H01L23/528 ,  H01L27/108

Abstract: The semiconductor structure has a layer structure formed from a metallic layer deposition (1) and a dielectric layer (2). The metallic layer deposition is structured and includes contact surface areas (3). The dielectric layer is composed of a removable material and covers the metallic layer deposition. The contact surface areas are formed from many connected single structures (4) which are so narrow, that the removable material forms no surface areas on the single structures, which proceed parallel to the metallic layer deposition. The single structures are preferably narrower than the double thickness, with which the dielectric layer is layered between structures of the metallic layer deposition.

公开(公告)号：DE19937504A1

公开(公告)日：2001-03-15

申请号：DE19937504

申请日：1999-08-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIESLICH ALBRECHT ,  BENZINGER HERBERT ,  FELDNER KLAUS

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/76

Abstract: A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an insulation. The method creates both the storage capacitors and the insulation by forming trenches in the first region and at least one trench in the second region, and the trenches have a depth of at least 2 mum. The trenches in the first region are treated to provide first and second electrodes separated by a dielectric to form the capacitors and each trench in the second region provides an insulation which surrounds any wells in the second region.

公开(公告)号：DE102004010902B4

公开(公告)日：2007-01-11

申请号：DE102004010902

申请日：2004-03-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NOELSCHER CHRISTOPH ,  KIESLICH ALBRECHT ,  PFORR RAINER ,  HENNIG MARIO

IPC: G03F1/30 ,  G03F7/20 ,  G03F9/00

Abstract: A mask level layout has an arrangement of lines and spaces with the spaces interconnected by a further space. The spaces are alternately acted upon with a phase deviation with respect to the spaces, where a phase edge between spaces acted upon differently arises in the region of the further space. Alternatively, the connecting space within the layout may be filled with dark regions. An additional space is inserted in a second layout representing a further mask of the same mask set. The additional space enables formation of an insulating region on a semiconductor substrate at the location where formation of a continuous isolation trench is not possible due to the phase edges or dark regions within originally connecting spaces of the first mask. The first mask can be embodied as a hybrid mask with structures according to the principle of alternating phase masks with a large process window.

公开(公告)号：DE102004010902A1

公开(公告)日：2005-09-22

申请号：DE102004010902

申请日：2004-03-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NOELSCHER CHRISTOPH ,  KIESLICH ALBRECHT ,  PFORR RAINER ,  HENNIG MARIO

IPC: G03F1/30 ,  G03F7/20 ,  G03F9/00 ,  G03F1/14

Abstract: A mask level layout has an arrangement of lines and spaces with the spaces interconnected by a further space. The spaces are alternately acted upon with a phase deviation with respect to the spaces, where a phase edge between spaces acted upon differently arises in the region of the further space. Alternatively, the connecting space within the layout may be filled with dark regions. An additional space is inserted in a second layout representing a further mask of the same mask set. The additional space enables formation of an insulating region on a semiconductor substrate at the location where formation of a continuous isolation trench is not possible due to the phase edges or dark regions within originally connecting spaces of the first mask. The first mask can be embodied as a hybrid mask with structures according to the principle of alternating phase masks with a large process window.

公开(公告)号：DE10331030B3

公开(公告)日：2005-03-03

申请号：DE10331030

申请日：2003-07-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PEARS KEVIN ,  KIESLICH ALBRECHT ,  KUDELKA STEFAN

IPC: H01L21/20 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242