公开(公告)号：EP2831749A4

公开(公告)日：2016-01-06

申请号：EP12873063

申请日：2012-03-30

Applicant: INTEL CORP

Inventor： CAPRIOLI PAUL ,  MERTEN MATTHEW C ,  AL-OTOOM MUAWYA M ,  SHAIKH OMAR M ,  KANHERE ABHAY S ,  SRINIVAS SURESH ,  YAMADA KOICHI ,  THAKKAR VIVEK ,  OSCIAK PAWEL

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06F13/14

CPC classification number: G06F11/3466 ,  G06F8/40 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/3842 ,  G06F9/4552 ,  G06F11/073 ,  G06F11/3616 ,  G06F11/3652

Abstract: A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

公开(公告)号：EP3234844A4

公开(公告)日：2018-08-01

申请号：EP15870567

申请日：2015-11-16

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  BIJLANI ASHISH ,  LU JIWEI ,  ZHAO CHENG YAN

IPC: G06F8/52 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F8/52 ,  G06F9/30054 ,  G06F9/30145

Abstract: A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.

公开(公告)号：EP3014423A4

公开(公告)日：2017-03-15

申请号：EP13887955

申请日：2013-06-28

Applicant: INTEL CORP

Inventor： SARKAR ABHIK ,  LU JIWEI ,  SHANMUGAVELAYUTHAM PALANIVELRAJAN RAJAN ,  AGRON JASON M ,  YAMADA KOICHI

IPC: G06F9/455 ,  G06F9/445 ,  G06F9/48 ,  G06F9/50 ,  G06F12/02 ,  G06F12/0802

CPC classification number: G06F9/5038 ,  G06F8/61 ,  G06F8/62 ,  G06F9/45516 ,  G06F9/485 ,  G06F9/5016 ,  G06F12/0253 ,  G06F12/0802 ,  G06F2212/1044 ,  G06F2212/60

Abstract: Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.

Abstract translation: 用于多核平台上部分二进制转换的技术包括共享转换缓存，二进制转换线程调度程序，全局安装线程以及每个处理器内核的本地转换线程和分析线程。 在检测到热点时，线程调度程序首先在挂起时恢复全局线程，接下来如果转换缓存操作正在等待，则激活全局线程，最后计划本地转换或分析线程执行。 翻译缓存操作集中在全局线程中，并与分析和翻译分离。 线程调度器可以在非优先级核中执行，并且转换和分析线程可以在抢占式运行时间内执行。 全局线程可能主要采用小型非抢占核来提交更新到共享转换缓存。 全局线程可能迁移到任何处理器内核。 前进进度得到保证。 描述和要求保护其他实施例。

公开(公告)号：EP1027654A4

公开(公告)日：2002-09-25

申请号：EP98906115

申请日：1998-02-04

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  HAMMOND GARY N

IPC: G06F12/10 ,  G06F12/06 ,  G06F12/08

CPC classification number: G06F12/1009 ,  G06F2212/652

Abstract: A method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area (315) and a page table walker. The page size storage area is used to store a number of page sizes selected for translating (305) a number of virtual addresses. The page table walker includes a selection unit (320) coupled to the page size storage area, as well as a page entry address generator (325) coupled to the selection unit. For each virtual address received by the selection unit, the selection unit positions a field in that virtual address based on the page size selected for translating that virtual address. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator (325) identifies an entry in a page table based on those bits.

公开(公告)号：DE602008000690D1

公开(公告)日：2010-04-08

申请号：DE602008000690

申请日：2008-03-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  COVELLI DOUGLAS ,  VARGAS JOSE ,  KUMAR MOHAN

IPC: G06F11/20

Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantially non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

公开(公告)号：DE69724572T2

公开(公告)日：2004-04-08

申请号：DE69724572

申请日：1997-05-23

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  HAMMOND GARY N

IPC: G06F12/10

公开(公告)号：AU6143198A

公开(公告)日：1998-10-22

申请号：AU6143198

申请日：1998-02-04

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  HAMMOND GARY N

IPC: G06F12/10 ,  G06F12/06 ,  G06F12/08

Abstract: A method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes selected for translating a number of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each virtual address received by the selection unit, the selection unit positions a field in that virtual address based on the page size selected for translating that virtual address. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.

公开(公告)号：AU2010337304B2

公开(公告)日：2016-02-04

申请号：AU2010337304

申请日：2010-10-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

IPC: G06F9/24 ,  G06F9/30 ,  G06F9/44 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

公开(公告)号：GB2519877B

公开(公告)日：2015-07-29

申请号：GB201500492

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/30 ,  G06F9/318 ,  G06F12/10

公开(公告)号：AT459047T

公开(公告)日：2010-03-15

申请号：AT08251110

申请日：2008-03-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  COVELLI DOUGLAS ,  VARGAS JOSE ,  KUMAR MOHAN

IPC: G06F11/20

Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantially non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.