公开(公告)号：US20170285280A1

公开(公告)日：2017-10-05

申请号：US15089524

申请日：2016-04-02

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/42 ,  G02B6/30 ,  G02B6/132 ,  G02B6/122

CPC classification number: G02B6/428 ,  G02B6/12002 ,  G02B6/122 ,  G02B6/1221 ,  G02B6/132 ,  G02B6/30 ,  G02B6/4232 ,  G02B6/4238 ,  G02B6/43 ,  G02B2006/12197

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US20170217766A1

公开(公告)日：2017-08-03

申请号：US15484765

申请日：2017-04-11

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US10816742B2

公开(公告)日：2020-10-27

申请号：US16182450

申请日：2018-11-06

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Sven Albers ,  Thomas Wagner ,  Marc Dittes ,  Klaus Reingruber ,  Andreas Wolter ,  Richard Patten

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/132 ,  G02B6/30 ,  G02B6/12 ,  G02B6/43

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

公开(公告)号：US10651102B2

公开(公告)日：2020-05-12

申请号：US15778410

申请日：2015-12-18

Applicant: Intel IP Corporation

Inventor： Klaus Reingruber ,  Christian Geissler ,  Georg Seidemann ,  Sonja Koller

IPC: H01L23/48 ,  H01L23/13 ,  H01L23/12 ,  H01L23/498 ,  H05K3/40 ,  H05K1/18

Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.

公开(公告)号：US10446541B2

公开(公告)日：2019-10-15

申请号：US15743996

申请日：2015-09-14

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Christian Geissler ,  Klaus Reingruber

IPC: H01L23/48 ,  H01L27/02 ,  H01L23/60 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L49/02 ,  H01L25/10 ,  H01L23/14 ,  H01L23/498

Abstract: An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.

公开(公告)号：US10373844B2

公开(公告)日：2019-08-06

申请号：US15590890

申请日：2017-05-09

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

公开(公告)号：US20170345678A1

公开(公告)日：2017-11-30

申请号：US15590890

申请日：2017-05-09

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

公开(公告)号：US20170256480A1

公开(公告)日：2017-09-07

申请号：US15062143

申请日：2016-03-06

Applicant: Intel IP Corporation

Inventor： Klaus Reingruber ,  Sven Albers ,  Christian Geissler

IPC: H01L23/498 ,  H05K1/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L21/48

Abstract: Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.

公开(公告)号：US09741651B1

公开(公告)日：2017-08-22

申请号：US15052505

申请日：2016-02-24

Applicant: Intel IP Corporation

Inventor： Klaus Reingruber ,  Sven Albers ,  Christian Geissler

IPC: H01F5/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L24/19 ,  H01L2224/04105

Abstract: Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a patterned metal redistribution layer (RDL) may be coupled with the second face of the dielectric layer. The line may include a first portion with a first width and a second portion directly coupled to the first portion, the second portion having a second width. The first portion may extend beyond a plane of the second face of the dielectric layer, and the second portion may be positioned between the first face and the second face of the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20170062306A1

公开(公告)日：2017-03-02

申请号：US14839510

申请日：2015-08-28

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Alexandra Atzesdorfer ,  Sonja Koller

IPC: H01L23/427 ,  H01L23/373

CPC classification number: H01L23/3737 ,  G06F1/203 ,  G06F2200/201 ,  H01L23/373 ,  H01L23/427 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及一种用于半导体器件的冷却器。 半导体器件可以电耦合到电源。 当设备使用期间电源向设备供电时，设备可能会产生热量。 冷却器可以联接到装置的一个或多个表面。 冷却器可以包括用于从环境空气中吸附水的亲水材料。 在设备运行期间，冷却器可以通过将热量从设备传导到冷却器来冷却设备。 冷却器可以包括在使用装置期间蒸发的水以增加冷却器的冷却能力。 当设备未在较低功率水平下操作或操作时，冷却器可能会在空气中从潮湿的水中充电。 可以描述和/或要求保护其他实施例。