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公开(公告)号：GB2497248B
公开(公告)日：2014-12-31
申请号：GB201305445
申请日：2011-07-20
Applicant: IBM
Inventor： AVOURIS PHAEDON , FARMER DAMON BROOKS , LIN YU-MING , ZHU YU
IPC: H01L29/16 , H01L29/417 , H01L29/423 , H01L29/778 , H01L29/786
Abstract: A method of forming a transistor structure is provided. The method includes forming a graphene layer on an insulating layer; forming a stack of a first metal portion and a second metal portion over the graphene layer, wherein sidewalls of the first metal portion are vertically coincident with sidewalls of the second metal portion; and laterally offsetting the sidewalls of the first metal portion relative to the sidewalls of the second metal portion by a lateral distance.
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公开(公告)号：GB2493238B
公开(公告)日：2014-04-16
申请号：GB201208558
申请日：2011-04-26
Applicant: IBM
Inventor： CHEN KUAN-NENG , LIN YU-MING , AVOURIS PHAEDON , FARMER DAMON BROOKS
IPC: H01L21/822 , B82Y10/00 , H01L27/06 , H01L27/12 , H01L29/16 , H01L29/786
Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.
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公开(公告)号：DE102013210161A1
公开(公告)日：2013-12-19
申请号：DE102013210161
申请日：2013-05-31
Applicant: IBM
Inventor： AVOURIS PHAEDON , GARCIA ALBERTO V , SUNG CHUN-YUNG , XIA FENGNIAN , YAN HUGEN
IPC: H01Q17/00
Abstract: Strukturen und Verfahren zum Verdecken eines Objekts vor elektromagnetischer Strahlung bei den Mikrowellen- und Terahertz-Frequenzen beinhalten das Aufbringen einer Vielzahl von dünnen Lagen aus Graphen um das Objekt herum. Zwischenschichten aus einem transparenten dielektrischen Material können zwischen den dünnen Lagen aus Graphen aufgebracht sein, um die Leistungsfähigkeit zu optimieren. In weiteren Ausführungsformen kann das Graphen in eine Anstrichformulierung oder ein Gewebe formuliert und an dem Objekt angebracht sein. Die Strukturen und Verfahren absorbieren wenigstens einen Anteil der elektromagnetischen Strahlung bei den Mikrowellen- und Terabyte-Frequenzen.
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公开(公告)号：GB2497248A
公开(公告)日：2013-06-05
申请号：GB201305445
申请日：2011-07-20
Applicant: IBM
Inventor： AVOURIS PHAEDON , FARMER DAMON BROOKS , LIN YU-MING , ZHU YU
IPC: H01L29/16 , H01L29/417 , H01L29/423 , H01L29/778 , H01L29/786
Abstract: A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode.
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公开(公告)号：AT551734T
公开(公告)日：2012-04-15
申请号：AT03721349
申请日：2003-02-19
Applicant: IBM
Inventor： APPENZELLER JOERG , AVOURIS PHAEDON , CHAN KEVIN , COLLINS PHILIP , MARTEL RICHARD , WONG HON-SUM PHILIP
Abstract: A carbon-nanotube field transistor semiconductor device, comprising: a vertical carbon-nanotube (508) wrapped in a dielectric material (511); a source formed at a first side of the carbon-nanotube; a drain (515) formed on a second side of the carbon-nanotube; a bilayer nitride complex through which a band strap of each of the source and the drain is formed connecting the carbon-nanotube wrapped in the dielectric material to the source and the drain; and a gate (512) formed substantially over a portion of the carbon-nanotube. Further disclosed are methods for forming the following self-aligned carbon-nanotube field effect transistor: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
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Patent Agency Ranking
公开(公告)号：AT516600T
公开(公告)日：2011-07-15
申请号：AT06120727
申请日：2003-02-19
Applicant: IBM
Inventor： APPENZELLER JOERG , AVOURIS PHAEDON , CHAN KEVIN K , COLLINS PHILIP G , MARTEL RICHARD , WONG HON-SUM
Abstract: A carbon-nanotube field transistor semiconductor device, comprising: a vertical carbon-nanotube (508) wrapped in a dielectric material (511); a source formed at a first side of the carbon-nanotube; a drain (515) formed on a second side of the carbon-nanotube; a bilayer nitride complex through which a band strap of each of the source and the drain is formed connecting the carbon-nanotube wrapped in the dielectric material to the source and the drain; and a gate (512) formed substantially over a portion of the carbon-nanotube. Further disclosed are methods for forming the following self-aligned carbon-nanotube field effect transistor: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
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公开(公告)号：AU2003279724A1
公开(公告)日：2004-04-19
申请号：AU2003279724
申请日：2003-09-26
Applicant: IBM
Inventor： COHEN GUY MOSHE , MARTEL RICHARD , MISEWICH JAMES A , TSANG JAMES CHEN-HSIANG , AVOURIS PHAEDON
Abstract: A light emitting device comprises a gate electrode, a channel comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode, a source coupled to a first end of the channel injecting electrons into the channel, and a drain coupled to a second end of the channel injecting holes into the channel.
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公开(公告)号：GB2507686B
公开(公告)日：2014-07-16
申请号：GB201402301
申请日：2011-04-26
Applicant: IBM
Inventor： CHEN KUAN-NENG , LIN YU-MING , AVOURIS PHAEDON , FARMER DAMON BROOKS
IPC: H01L29/16 , H01L21/822
Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.
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公开(公告)号：GB2507686A
公开(公告)日：2014-05-07
申请号：GB201402301
申请日：2011-04-26
Applicant: IBM
Inventor： CHEN KUAN-NENG , LIN YU-MING , AVOURIS PHAEDON , FARMER DAMON BROOKS
IPC: H01L29/16 , H01L21/822
Abstract: Graphene-channel based transistor comprising a substrate with a source and a drain contact 2102, and a graphene channel 2502 formed on the substrate 1704 which connects the contacts. A gate contact 2902 over the graphene channel, separated from the channel with a dielectric. The gate contact is positioned in a non-overlapping position with the source and drain contacts; this leaves exposed sections 3102 of the graphene channel, which can then be doped with an n-type or p-type dopant 3302. A capping layer may be provided over the source, drain and gate contacts, as well as the exposed sections of the graphene channel. The substrate may comprise an insulating layer on the channel. The substrate may comprise an insulating wafer or a wafer having an insulating over layer or a silicon carbide layer. The capping layer may comprise an oxide or a nitride material. There may be more than one layer of graphene on the substrate and this may be deposited using exfoliation or by silicon sublimation with epitaxy.
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公开(公告)号：SG184823A1
公开(公告)日：2012-11-29
申请号：SG2012075578
申请日：2011-04-26
Applicant: IBM
Inventor： CHEN KUAN-NENG , LIN YU-MING , AVOURIS PHAEDON , FARMER DAMON BROOKS
Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.
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