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    Self-aligned edge passivation for robust resistive random access memory connection
    22.
    发明专利
    Self-aligned edge passivation for robust resistive random access memory connection 未知

    公开(公告)号：GB2606919B

    公开(公告)日：2025-04-16

    申请号：GB202209965

    申请日：2020-12-14

    Applicant: IBM

    Inventor： TAKASHI ANDO ,  RUILONG XIE ,  POUYA HASHEMI ,  ALEXANDER REZNICEK

    IPC: H10N70/00 ,  H10N70/20

    Abstract: A resistive random access memory (RRAM) structure includes top and bottom electrodes electrically coupled with first and second metal connection lines, respectively, the first and second metal connection lines providing electrical connection to the RRAM structure. A layer of resistive switching material is disposed between the top and bottom electrodes of the RRAM structure. The resistive switching material exhibits a measurable change in resistance under influence of at least an electric field and/or heat. Dielectric spacers are formed on sidewalls of at least the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer formed on an upper surface of the dielectric spacers and covering at least a portion of sidewalls of the top electrode. The passivation layer is self-aligned with the first metal connection line.

    Three dimensional cross-point non-volatile memory
    23.
    发明专利
    Three dimensional cross-point non-volatile memory 未知

    公开(公告)号：GB2634478A

    公开(公告)日：2025-04-09

    申请号：GB202500991

    申请日：2023-07-31

    Applicant: IBM

    Inventor： CHANRO PARK ,  JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG

    IPC: H10B63/00 ,  H10N70/20

    Abstract: A non-volatile memory having a 3D cross-point architecture and twice the cell density is provided in which vertically stacked word lines run in plane (i.e., parallel) to the substrate and bit lines runs perpendicular to the vertically stacked word lines. The vertically stacked word lines are located in a patterned dielectric material stack that includes alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layers vertically separate each word line within each vertical stack of word lines and the recessed second dielectric material layers are located laterally adjacent to the word lines. A dielectric switching material layer is located between each word line-bit line combination. Some of the bit lines are located in the dielectric material stack and some of the bit lines are located in an interlayer dielectric material layer.

    CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation
    25.
    发明专利
    CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation 未知

    公开(公告)号：GB2631071A

    公开(公告)日：2024-12-18

    申请号：GB202414743

    申请日：2023-03-23

    Applicant: IBM

    Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK ,  OLEG GLUSCHENKOV

    IPC: H01L29/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

    Abstract: A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

    Self-aligned gate isolation with asymmetric cut placement
    26.
    发明专利
    Self-aligned gate isolation with asymmetric cut placement 未知

    公开(公告)号：GB2600316B

    公开(公告)日：2023-05-24

    申请号：GB202200795

    申请日：2020-06-15

    Applicant: IBM

    Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  VEERARAGHAVAN BASKER

    IPC: H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

    Abstract: A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.

    Nanosheet transistors with wrap around contact
    27.
    发明专利
    Nanosheet transistors with wrap around contact 未知

    公开(公告)号：GB2603283B

    公开(公告)日：2023-01-18

    申请号：GB202117763

    申请日：2021-12-09

    Applicant: IBM

    Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

    Abstract: An embodiment includes a method of forming a semiconductor device and the resulting device. The method may include forming a source/drain on an exposed portion of a semiconductor layer of a layered nanosheet. The method may include forming a sacrificial material on the source/drain. The method may include forming a dielectric layer covering the sacrificial material. The method may include replacing the sacrificial material with a contact liner. The semiconductor device may include a first gate nanosheet stack and second gate nanosheet stack. The semiconductor device may include a first source/drain in contact with the first nanosheet stack and a second source/drain in contact with the second nanosheet stack. The semiconductor device may include a source/drain dielectric located between the first source/drain and the second source/drain. The semiconductor device may include a contact liner in contact with the first source/drain, the second source/drain and the source/drain dielectric.

    Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions
    28.
    发明专利
    Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions 未知

    公开(公告)号：GB2595125B

    公开(公告)日：2022-11-09

    申请号：GB202111358

    申请日：2020-02-24

    Applicant: IBM

    Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS JEAN LOUBET

    IPC: H01L29/41

    Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

    Forming self-aligned contacts
    29.
    发明专利
    Forming self-aligned contacts 未知

    公开(公告)号：GB2579487A

    公开(公告)日：2020-06-24

    申请号：GB202001682

    申请日：2018-07-16

    Applicant: IBM ,  GLOBALFOUNDRIES INC ,  SAMSUNG ELECTRONICS CO LTD

    Inventor： SU CHEN FAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ANDREW GREENE ,  RUILONG XIE ,  MARK VICTOR RAYMOND ,  SEAN LIAN

    IPC: H01L21/8238

    Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided, in one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers In a dielectric; forming gate trenches by selectively rernoving the dielectric from: regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

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