公开(公告)号：DE3676620D1

公开(公告)日：1991-02-07

申请号：DE3676620

申请日：1986-10-07

Applicant: IBM

Inventor： CULICAN EDWARD FRANCIS ,  PRITZLAFF JR ,  VAN GOOR KENNETH ALAN ,  SCHETTLER HELMUT

IPC: H03K19/0175 ,  H03K17/60 ,  H03K19/013 ,  H03K19/018 ,  H03K19/088 ,  H03K19/082

Abstract: Circuitry for enhancing the ability of digital circuits to drive highly capacitive loads is disclosed. This circuitry has particular utility when employed with logic circuits such as "TTL" (Transistor- Transistor Logic) and "DTL" (Diode-Transistor Logic). … The circuitry (15) comprises four transistors (T1, T2, T3A, T3B) and two resistors (R1, R2), at least one of the transistors (T1, T3A) being connected as a diode.

公开(公告)号：CA1275508C

公开(公告)日：1990-10-23

申请号：CA554556

申请日：1987-12-16

Applicant: IBM

Inventor： KLEIN KLAUS ,  POLLMANN KURT ,  SCHETTLER HELMUT ,  SCHULZ UWE ,  WAGNER OTTO M ,  ZUEHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L21/822 ,  H01L27/04 ,  G06F15/60

Abstract: HIERARCHICAL TOP-DOWN METHOD FOR PHYSICAL VLSI-CHIP DESIGN For the physical design of a VLSI chip a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip needs no extra space for global wiring and the partitions are immediately attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.

公开(公告)号：DE2966357D1

公开(公告)日：1983-12-01

申请号：DE2966357

申请日：1979-11-19

Applicant: IBM

Inventor： SCHETTLER HELMUT ,  BROSCH RUDOLF DR ,  ZUEHLKE RAINER DR ,  SCHUMACHER HANS DR

IPC: H03K19/0175 ,  G05F1/46 ,  H03K5/00 ,  H03K5/13

Abstract: For equalizing the signal delay times of semiconductor chips a digital control circuit is provided on each chip. By altering the supply voltage, the digital control circuit influences the signal delay times. The digital control circuit comprises a comparator circuit where the signal delay of a clock pulse is compared in a chain of inverters with the very precisely defined clock interval. Depending on the result of the comparison, the count of an up-down counter is incremented or decremented by one. The resulting count is decoded and converted into a corresponding voltage for operating the circuits of the semiconductor chip. Subsequently, the above described steps are repeated until the difference DELTA t between the arrival of a clock pulse delayed by the chain, and the following undelayed clock pulse approaches zero.

公开(公告)号：MY130151A

公开(公告)日：2007-06-29

申请号：MYPI9001368

申请日：1990-08-15

Applicant: IBM

Inventor： SCHETTLER HELMUT ,  SCHULZ UWE ,  ZUHLKE RAINER

IPC: H01L23/538 ,  H01L23/14

Abstract: A SYSTEM DESIGN FOR VLSI CHIPS ARRANGED ON A CARRIER AND THE MODULE THUS DESIGNED IS DESCRIBED. IN A TOP-DOWN DESIGN SYSTEM SYNOPTICALLY AND SIMULTANEOUSLY AN ELECTRICAL CIRCUITRY IS OPTIMIZED BY DESIGNING SYNOPTICALLY THE CHIPS AND THE CHIP CARRIER. THE OVERALL LOGIC IS DIVIDED IN PARTITIONS WHICH FIT ON CHIPS. A CHIP PLACEMENT ON THE CARRIER IS PERFORMED CONSIDERING MINIMUM OVERALL CONNECTION LENGTH AND PROVIDING PREFERABLY PARALLEL CONNECTION. INPUT/OUTPUT CONTACTS ARE ASSIGNED ON CHIPS VIS-A-VIS EACH OTHER WHEN THEY CORRESPOND. THEY ARE CONNECTED BY PARALLEL LINES. THE DESIGN OF THE SEVERAL CHIPS IS DONE FROM OUTSIDE TO INSIDE, STARTING WITH THE ASSIGNED I/O CONTACTS. OVERALL, IN COMBINING OPTIMUM OVERALL DESIGN AND OPTIMUM CHIP DESIGN, A SEMICONDUCTOR THIN FILM SILICON MULTICHIP MODULE OF HIGH YIELD AND PERFORMANCE IS PROVIDED. AS CARRIER THAT IS INCLUDED IN THE DESIGN FROM THE BEGINNING, PREFERABLY A THIN FILM PASSIVE SILICON CARRIER IS USED.(FIG 6)

公开(公告)号：DE60109944D1

公开(公告)日：2005-05-12

申请号：DE60109944

申请日：2001-07-28

Applicant: IBM

Inventor： KROELL KARL-EUGEN ,  PILLE JUERGEN ,  SCHETTLER HELMUT

IPC: G06F17/50 ,  G06F19/00 ,  H01L29/00

公开(公告)号：DE3682043D1

公开(公告)日：1991-11-21

申请号：DE3682043

申请日：1986-12-02

Applicant: IBM

Inventor： BERANGER LEONARD HERVE ,  GAUDENZI GENE JOSEPH ,  REEDY DENNIS CONWAY ,  SCHETTLER HELMUT

IPC: H03K19/0175 ,  H03K17/16 ,  H03K19/003 ,  H03K19/018 ,  H03K19/0185 ,  H03K19/088 ,  H03K5/02

Abstract: A small signal swing line driver (100), that generates a reduced amount of switching noise and also suppresses transients appearing on the line, is described. Specifically, the driver (100) includes a clamp (200) connected to the driver output to limit the maximum DC driver output level and to suppress voltage transients, e.g. reflections, spikes or the like, appearing on the driven line and caused by conditions external to the driver (100). The driver (100) also contains circuitry to limit the transition times of the rising and falling edges of the driver output signal in order to reduce the amount of switching noise which is generated by the driver (100) and thereafter coupled onto quiet lines.

公开(公告)号：ES2021268B3

公开(公告)日：1991-11-01

申请号：ES86114537

申请日：1986-10-21

Applicant: IBM

Inventor： LUDWIG THOMAS ,  SCHETTLER HELMUT ,  ZUEHLKE RAINER ,  WAGNER OTTO

IPC: H03K4/02 ,  H03G11/00 ,  H03K5/02 ,  H03K6/04 ,  H03K17/16 ,  H03K19/0185

公开(公告)号：CA1261011A

公开(公告)日：1989-09-26

申请号：CA548403

申请日：1987-10-01

Applicant: IBM

Inventor： LUDWIG THOMAS ,  SCHETTLER HELMUT ,  WAGNER OTTO ,  ZUHLKE RAINER

IPC: H03K4/02 ,  H03G11/00 ,  H03K5/02 ,  H03K6/04 ,  H03K17/16 ,  H03K19/0185 ,  H03G11/08

Abstract: METHOD FOR THE DIGITAL SLOPE CONTROL OF THE OUTPUT SIGNALS OF POWER AMPLIFIERS OF SEMICONDUCTOR CHIPS WITH VLSI CIRCUITS FOR A COMPUTER A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method are described. One way of representing the actual slope value is via the number of clock pulses applied to a counter (10) during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator (1) containing one of the power amplifiers (2) to another counter (9) until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator (1) during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register (19). Its parallel outputs (21) influence via control line (22) control inputs (23) of the power amplifiers in order to alter their slope by switching on or off output transistors arranged in parallel with respect to their switching paths.

公开(公告)号：DE3063949D1

公开(公告)日：1983-08-04

申请号：DE3063949

申请日：1980-04-25

Applicant: IBM

Inventor： KRUMM HORST DR ,  SCHETTLER HELMUT ,  STAHL RAINER ,  ZUHLKE RAINER DR

IPC: H01L23/52 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14

Abstract: Disclosed is a multi-layer module structure having a constant characteristic impedance. In each conductor line plane, two signal lines are arranged between a ground and a voltage supply line. This line sequence: ground/signal/signal/voltage supply line, is repeated several times in each conductor line plane. The spacing between the signal line and the adjacent ground and voltage supply line, respectively, is identical in each case. Adjacent conductor line planes, nth and (n+1)th have conductor lines arranged orthogonally. The lines of the nth and the (n+2)th plane are preferably staggered to each other such that when the nth plane is projected relative to the (n+2)th plane, the ground line of the (n+2)th plane is arranged in between the voltage supply lines (e.g. a voltage supply line and a ground line) of the nth plane.