公开(公告)号：JP2001007223A

公开(公告)日：2001-01-12

申请号：JP2000160941

申请日：2000-05-30

Applicant: IBM

Inventor： JEFFREY P GANBINO ,  LEWIS L SUU ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function gate conductor having a self-aligned insulating cap, and a method for forming the dual work function gate conductor. SOLUTION: Two diffusion regions 36 are formed on a substrate 20, and gate stacks 33 and 34 are formed on the substrate 20 between these regions 36. The stacks 33 and 34 have a gate insulating layer 24, and polysilicon layers 26 and 26a on the layer 24, respectively. The layers 26 and 26a are n-type doped and remain intrinsic. A barrier layer 28 is formed on each of the layers 26 and 26a. A dopant source 30 is formed on the layer 28 for both stacks 33 and 34. The layer 28 has a p-type dopant. The stacks 33 and 34 are covered with an insulating cap 32 so that diffusion contacts can be formed on the gates in a borderless manner. When to start activating the source 30 for doping the layers 26 and 26a can be postponed until the desired timing.

公开(公告)号：DE60236375D1

公开(公告)日：2010-06-24

申请号：DE60236375

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J ,  FRIED DAVID M

IPC: H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

公开(公告)号：AU2002368525A1

公开(公告)日：2004-07-22

申请号：AU2002368525

申请日：2002-12-20

Applicant: IBM

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M ,  RANKIN JED H

IPC: H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12 ,  H01L21/44

公开(公告)号：MY134452A

公开(公告)日：2007-12-31

申请号：MYPI20054051

申请日：2001-05-23

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  DIVAKARUNI RAMACHANDRA ,  HOUGHTON RUSSELL J ,  MANDELMAN JACK A ,  TONTI WILLIAM R

IPC: H01L21/336 ,  H01L21/82 ,  H01L21/00 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: AN ANTI-FUSE STRUCTURE THAT CAN BE PROGRAMMED AT LOW VOLTAGE AND CURRENT AND WHICH POTENTIALLY CONSUMES VERY LITTLE CHIP SPACES AND CAN BE FORMED INTERSTITIALLY BETWEEN ELEMENTS SPACED BY A MINIMUM LITHOGRAPHIC FEATURE SIZE IS FORMED ON A COMPOSITE SUBSTRATE SUCH AS A SILICON-ONINSULATOR WAFER BY ETCHING A CONTACT THROUGH AN INSULATOR TO A SUPPORT SEMICONDUCTOR LAYER, PREFERABLY IN COMBINATION WITH FORMATION OF A CAPACITOR-LIKE STRUCTURE REACHING TO OR INTO THE SUPPORT LAYER. THE ANTI-FUSE MAY BE PROGRAMMED EITHER BY THE SELECTED LOCATION OF CONDUCTOR FORMATION AND/OR DAMAGING A DIELECTRIC OF THE CAPACITOR-LIKE STRUCTURE. AN INSULATING COLLAR (38, 90) IS USED TO SURROUND A PORTION OF EITHER THE CONDUCTOR (42, 100) OR THE CAPACITOR-LIKE STRUCTURE TO CONFINE DAMAGE TO THE DESIRED LOCATION.HEATING EFFECTS VOLTAGE AND NOISE DUE TO PROGRAMMING CURRENTS ARE EFFECTIVELY ISOLATED TO THE BULK SILICON LAYER, PERMITTING PROGRAMMING DURING NORMAL OPERATION OF THE DEVICE. THUS THE POTENTIAL FOR SELF-REPAIR WITHOUT INTERRUPTION OF OPERATION IS REALIZED.(FIG 6)

公开(公告)号：AU2003304110A1

公开(公告)日：2004-11-26

申请号：AU2003304110

申请日：2003-04-30

Applicant: IBM

Inventor： TONTI WILLIAM R ,  BERRY WAYNE S ,  FIFIELD JOHN A ,  GUTHRIE WILLIAM H ,  KONTRA RICHARD S

IPC: H01L23/525 ,  H01L29/00 ,  H01L21/44

Abstract: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

公开(公告)号：JP2007053400A

公开(公告)日：2007-03-01

申请号：JP2006289044

申请日：2006-10-24

Applicant: Infineon Technol North America Corp ,  Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  インフィニオン テクノロジーズ ノース アメリカ コーポレイション Infineon Technologies North America Corp.

Inventor： YE QIUYI ,  TONTI WILLIAM R ,  LI YUJUN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/10888 ,  H01L21/76897 ,  H01L27/10894

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function semiconductor structure with borderless contact and a method for manufacturing the same.
SOLUTION: The structure may comprise a substantially cap-free gate 108 and conductive contacts 134 and 170 to a diffusion part 116 adjacent to the cap-free gate, and the conductive contact may include a field effect transistor (FET) borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有无边界接触的双功能半导体结构及其制造方法。 解决方案：该结构可以包括基本无盖的栅极108和导电触点134和170，其连接到与无盖盖栅极相邻的扩散部分116，并且导电触点可以包括无边界的场效应晶体管（FET） 大门。 由于该结构是双重功能结构，所以允许导电接触件在无盖栅极上延伸而不与其电连接。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006172451A

公开(公告)日：2006-06-29

申请号：JP2005344698

申请日：2005-11-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BONACCIO ANTHONY R ,  ERICKSON KARL R ,  FIFIELD JOHN A ,  KOTHANDARAMAN CHANDRASEKHARAN ,  PAONE PHIL C ,  TONTI WILLIAM R

IPC: G06F21/06 ,  H01L21/822 ,  H01L27/04 ,  H03K19/173

CPC classification number: G06F12/1433 ,  G06F21/6245

Abstract: PROBLEM TO BE SOLVED: To provide a method and system, in which operation of and/or access to a particular function of an electronic device can be controlled after the device leaves the control of the manufacturer. SOLUTION: Techniques and systems whereby the operation and/or the access to the particular function of the electronic device cany be controlled after the device leaves the control of the manufacturer are provided. The operation and/or access can be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES). COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在设备离开制造商的控制之后可以控制电子设备的特定功能的操作和/或访问的方法和系统。 解决方案：提供了在设备离开制造商的控制之后操作和/或访问电子设备的特定功能的技术和系统。 操作和/或访问可以基于存储在诸如电可编程熔丝（eFUSES）的非易失性存储元件中的值来提供。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004111957A

公开(公告)日：2004-04-08

申请号：JP2003310635

申请日：2003-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  FREY ULRICH ,  HEGDE SURYANARAYAN G ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide the structure and the method of forming an integrated circuit including a low programming voltage anti-fuse on a semiconductor substrate. SOLUTION: This integrated circuit is formed by doping a part of a semiconductor substrate with nitrogen and a charge carrier dopant source, forming a thin dielectric that is destroyed by the application of breakdown voltage on the doped portion of the semiconductor substrate, forming a first conductor that is separated from the semiconductor substrate by the thin dielectric, and forming a second conductor that is conductively connected with the doped portion of the semiconductor substrate. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002261599A

公开(公告)日：2002-09-13

申请号：JP2001368652

申请日：2001-12-03

Applicant: IBM

Inventor： ANAND DARREN L ,  JOHN EDWARD BASS JR ,  FIFIELD JOHN ATKINSON ,  GILLIS PAMELA SUE ,  JAKOBSEN PETER O ,  KEMERER DOUGLAS WAYNE ,  LACKEY DAVID E ,  OAKLAND STEVEN FREDERICK ,  OUELLETTE MICHAEL RICHARD ,  TONTI WILLIAM R

IPC: H01L21/82 ,  G11C7/00 ,  G11C29/00 ,  G11C29/04 ,  H03K19/173

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for a fuse programming integrated circuit in which fuses are used in common by redundant elements. SOLUTION: A method and a device for initializing an integrated circuit by the use of the compressed data from a remote fuse box are capable of reducing fuses in number required for repairing or customizing the integrated circuit, and grouping the fuses outside macros which are repaired by the fuses. The remote position of the fuses improves the arrangement of the macros, having redundant repairing performances in flexibility and enables the fuses to be properly grouped for facilitating the usability of programming and the layout of circuits. The fuses are formed into columns and rows, to represent control words and run-length compressed data and to provide more repairing points per fuse. The data are loaded into a shift register in series and shifted to macro positions, for controlling the selection of redundant circuits, so that defective integrated circuits can be repaired, and the logic is customized.

公开(公告)号：JP2001274343A

公开(公告)日：2001-10-05

申请号：JP2001048615

申请日：2001-02-23

Applicant: IBM

Inventor： GAUTHIER JR ROBERT J ,  SCHEPIS DOMINIC J ,  TONTI WILLIAM R ,  VOLDMAN STEVEN H

IPC: H01L27/04 ,  H01L21/762 ,  H01L21/763 ,  H01L21/822 ,  H01L23/367 ,  H01L27/00 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure wherein the thermal conductivity is enhanced, and its manufacturing method. SOLUTION: During manufacturing of selected electronic components, silicon is formed at selected position on a substrate. Dielectric isolation regions are formed in an upper silicon layer and filled with a thermal conductive material. Before depositing the thermal conductive material, a liner material may be deposited at option. In a second embodiment, a horizontal layer of the thermal conductive material is deposited in an oxide layer or bulk silicon layer beneath the upper silicon layer.