公开(公告)号：DE10051719C2

公开(公告)日：2003-10-02

申请号：DE10051719

申请日：2000-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLING SABINE ,  SAVIGNAC DOMINIQUE ,  MOLL HANS-PETER ,  HAFFNER HENNING ,  HIETSCHOLD ELKE

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/02 ,  H01L27/105 ,  H01L21/312 ,  H01L21/8239 ,  H01L27/108

Abstract: The method involves using a lithographic process, whereby photo-lacquer structures are formed on the semiconducting substrate (5) to define dummy circuit structures. If an envisaged dummy structure (4) is smaller than a minimum size determined by the smallest required adhesive surface for photo-lacquer the first dummy structure is combined with a second to exceed the minimum size. An independent claim is also included for the following: a semiconducting substrate with functional circuit structures and dummy structures.

公开(公告)号：DE59914589D1

公开(公告)日：2008-02-07

申请号：DE59914589

申请日：1999-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WIRTH NORBERT ,  CORDES ERIC ,  MANYOKI ZOLTAN ,  SAVIGNAC DOMINIQUE

IPC: G01R31/316 ,  G01R31/28

Abstract: The component (5) can be connected to a burn-in voltage, which is higher than its internal voltage, which is impressed across a switchable regulator (6) integrated in the component. An element (1,2) integrated in the component has a different characteristic, e.g. degradation, from the regulator under the burn-in voltage after the burn-in test duration. The element may be a fuse.

公开(公告)号：DE102005051943A1

公开(公告)日：2006-07-06

申请号：DE102005051943

申请日：2005-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

IPC: G11C7/10

Abstract: The present invention relates to an integrated memory device including: memory cells arranged at wordlines and bitlines, wherein the memory cells are addressable in sets of 2 n bit, wherein n is an integer, a pre-fetch read unit to pre-fetch an addressed set of 2 n data bit in parallel from the addressed memory area, buffer memory to buffer the number of pre-fetched data bits; a number m of output ports to output the data bits buffered in the buffer memory; an output controller for controlling the outputting of the data bits buffered in the buffer memory to the number m of output ports in groups of m bits in one or a plurality of successive cycles, characterized in that the number m of output ports is different to any of the possible numbers 2 n of the sets of addressable memory cells.

公开(公告)号：DE10124752B4

公开(公告)日：2006-01-12

申请号：DE10124752

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  CHRYSOSTOMIDES ATHANASIA

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/18

Abstract: The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.

公开(公告)号：DE10124753A1

公开(公告)日：2002-12-12

申请号：DE10124753

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  CHRYSOSTOMIDES ATHANASIA ,  KLING SABINE

IPC: G11C7/06

Abstract: The method involves applying a binary memory cell signal(s) to a bit line pair(s), connecting the signal to a detection amplifier(s) depending on a cell field control signal(s), connecting a binary output signal to a local data line pair as a binary intermediate signal depending on a column control signal, connecting the intermediate signal to a main data line pair(s) depending on a line control signal and outputting a binary output signal. The method involves applying at least one binary memory cell signal to at least one bit line pair (201t,201b), connecting the signal to at least one detection amplifier (202-0 to 202-7) depending on at least one cell field control signal, connecting a binary output signal to a local data line pair as a binary intermediate signal depending on a column control signal, connecting the intermediate signal to at least one main data line pair depending on a line control signal and outputting a binary output signal

公开(公告)号：DE10123594A1

公开(公告)日：2002-11-28

申请号：DE10123594

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/085

Abstract: The circuit includes MOSFETs (1-4) having different average switching frequencies. The transistors have dielectric layers made of gate oxide, adjacent to gate electrodes. The thickness of the dielectric layers in the MOSFETs (1,3), is less than that of the dielectric layers in the MOSFETs (2,4).

公开(公告)号：DE10058966A1

公开(公告)日：2002-06-13

申请号：DE10058966

申请日：2000-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE

IPC: G11C7/22 ,  G11C11/4074 ,  G11C11/406

Abstract: The method involves supplying the memory cells (14) with electrical charge at defined time intervals during a refresh process. Memory cells are selected and the refresh process is only carried out for the selected memory cells. The memory (15) is divided into defined areas of memory cells, an area is selected and a refresh process carried out only for the cells in this area. Independent claims are also included for the following: a memory component with a memory field.

公开(公告)号：DE19962677A1

公开(公告)日：2001-07-05

申请号：DE19962677

申请日：1999-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ROBERT ,  SAVIGNAC DOMINIQUE

IPC: G01R31/28 ,  G01R31/3185 ,  G11C11/401 ,  G11C29/56 ,  H01L21/66

Abstract: The configuration allows for testing a multiplicity of semiconductor chips with respect to critical parameters on the wafer level. Each of the semiconductor chips on a semiconductor wafer is additionally provided with at least one option pad. The option pad allows access for a test program to the chip for separating out the semiconductor chips which do not correspond to predetermined requirements for critical parameters.

公开(公告)号：DE19961790C1

公开(公告)日：2001-05-10

申请号：DE19961790

申请日：1999-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE

IPC: H01L21/301 ,  H01L23/31 ,  H01L21/78 ,  H01L23/525 ,  H01L21/304

Abstract: The separation device separates a semiconductor chip from a semiconductor wafer having an insulation layer (3) provided with a number of metallisation planes (M0,M1,M2), in which a recess (5) is provided for reducing the thickness of the insulation layer to define a separation line. The insulation layer is provided by a silicon dioxide layer, which is provided with openings for electrical connection of the uppermost metallisation plane (M2) with the underlying metallisation plane (M1) via a connection layer (C2), together with the recess for reducing the thickness of the insulation layer.

公开(公告)号：FR2978591A1

公开(公告)日：2013-02-01

申请号：FR1202102

申请日：2012-07-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIRSCHL THOMAS ,  OTTERSTEDT JAN ,  SAVIGNAC DOMINIQUE ,  ALLERS WOLF

IPC: G11C7/12

Abstract: Mémoire (100) qui comprend une cellule (102) de mémoire, un élément (104) d'accumulation d'énergie configuré pour prendre en charge une programmation de la cellule (100) de mémoire, une alimentation (106) en énergie reliée à l'élément (104) d'accumulation d'énergie et une unité (108) de commande configurée pour activer l'alimentation (106) en énergie.