公开(公告)号：DE602006014596D1

公开(公告)日：2010-07-08

申请号：DE602006014596

申请日：2006-12-15

Applicant: INTEL CORP

Inventor： PETERSEN LEAF ,  SAHA BRATIN ,  ADL-TABATABAI ALI-REZA

IPC: G06F11/14

公开(公告)号：AT420400T

公开(公告)日：2009-01-15

申请号：AT04815332

申请日：2004-12-21

Applicant: INTEL CORP

Inventor： SHPEISMAN TATIANA ,  ADL-TABATABAI ALI-REZA

IPC: G06F9/45 ,  G06F9/00 ,  G06F12/00

Abstract: In one embodiment, a method is provided. The method of this embodiment provides scheduling a sequence of machine-executable instructions, and creating a data layout based on the scheduled sequence of machine-executable instructions.

公开(公告)号：DE602004016882D1

公开(公告)日：2008-11-13

申请号：DE602004016882

申请日：2004-12-08

Applicant: INTEL CORP

Inventor： SERRANO MAURICIO ,  SUBRAMONEY SREENIVAS ,  HUDSON RICHARD ,  ADL-TABATABAI ALI-REZA

IPC: G06F9/45 ,  G06F12/02

Abstract: Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.

公开(公告)号：AU2010337304B2

公开(公告)日：2016-02-04

申请号：AU2010337304

申请日：2010-10-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

IPC: G06F9/24 ,  G06F9/30 ,  G06F9/44 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

公开(公告)号：GB2519877B

公开(公告)日：2015-07-29

申请号：GB201500492

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/30 ,  G06F9/318 ,  G06F12/10

公开(公告)号：AT469394T

公开(公告)日：2010-06-15

申请号：AT06845638

申请日：2006-12-15

Applicant: INTEL CORP

Inventor： PETERSEN LEAF ,  SAHA BRATIN ,  ADL-TABATABAI ALI-REZA

IPC: G06F11/14

公开(公告)号：DE602004020668D1

公开(公告)日：2009-05-28

申请号：DE602004020668

申请日：2004-12-03

Applicant: INTEL CORP

Inventor： SUBRAMONEY SREENIVAS ,  SERRANO MAURICIO ,  HUDSON RICHARD ,  ADL-TABATABAI ALI-REZA

IPC: G06F9/45 ,  G06F12/02

公开(公告)号：DE102007006190A1

公开(公告)日：2007-08-30

申请号：DE102007006190

申请日：2007-02-07

Applicant: INTEL CORP

Inventor： JACOBSON QUINN ,  BRACY ANNE ,  WANG HONG ,  SHEN JOHN ,  HAMMARLUND PER ,  MERTEN MATTHEW ,  SRINIVAS SURESH ,  DOSHI KSHITIJ ,  CHINYA GAUTHAM ,  SAHA BRATIN ,  ADL-TABATABAI ALI-REZA ,  SHEAFFER GAD

IPC: G06F12/02 ,  G06F12/00

Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.

公开(公告)号：DE102007006190B4

公开(公告)日：2017-10-26

申请号：DE102007006190

申请日：2007-02-07

Applicant: INTEL CORP

Inventor： JACOBSON QUINN ,  BRACY ANNE ,  WANG HONG ,  SHEN JOHN ,  HAMMARLUND PER ,  MERTEN MATTHEW ,  SRINIVAS SURESH ,  DOSHI KSHITIJ ,  CHINYA GAUTHAM ,  SAHA BRATIN ,  ADL-TABATABAI ALI-REZA ,  SHEAFFER GAD

IPC: G06F12/02 ,  G06F12/00

Abstract: Maschinenlesbares Medium, auf dem ein Satz Befehle gespeichert ist, die, wenn sie von einer Maschine ausgeführt werden, die Maschine dazu veranlassen, ein Verfahren auszuführen, das aufweist: Lesen eines Attributbits (115), welches einer Cache-Speicherlinie (105) zugeordnet ist, wobei die Cache-Speicherlinie (105) nur einem Software-Thread in einem Multi-Thread-Programm zugeordnet ist, wobei das Attributbit (115) als ein Ergebnis des Ausführens eines Befehls geprüft wird, und wobei das Attributbit (115) durch Ausführen eines load_check Befehls gelesen wird und das Attributbit durch Ausführen eines load_set Befehls gesetzt wird; Bestimmen des Werts des Attributbits (115), wobei das Bestimmen des Werts des Attributbits (115) das Ausführen eines Architekturszenarios in einem Prozessor der Maschine aufweist, wobei das Szenario bestimmt, ob die Cache-Speicherlinie (115) sich in einem unerwarteten Zustand befindet; Ausführen eines leichtgewichtigen Yield-Ereignisses in Reaktion auf das Bestimmen des Werts des Attributbits (115).

公开(公告)号：BRPI0925055A2

公开(公告)日：2015-07-28

申请号：BRPI0925055

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/06 ,  G06F9/44 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/00 ,  G06F15/00