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    直插式芯片焊座及直插式芯片组装结构
    22.
    发明公开
    直插式芯片焊座及直插式芯片组装结构 失效

    公开(公告)号：CN101296560A

    公开(公告)日：2008-10-29

    申请号：CN200710200565.4

    申请日：2007-04-29

    Applicant: 佛山普立华科技有限公司 ,  鸿海精密工业股份有限公司

    Inventor： 侯震 ,  王境良

    IPC: H05K1/02 ,  H01R12/00

    CPC classification number: H01R43/0256 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09463 ,  H05K2201/09709 ,  H05K2201/10689 ,  H05K2201/10696

    Abstract: 本发明提供一种直插式芯片焊座，其包括一个具有一个焊接面的基板、至少一个开设于所述焊接面的插设部及至少一个形成于所述焊接面的焊盘组。每个插设部用于收容待组装直插式芯片的一列插脚，每个焊盘组包括多个位于对应插设部边缘的焊盘，用于焊接待组装直插式芯片的一列插脚。同个焊盘组中，用于焊接待组装直插式芯片相邻两只插脚的两个焊盘分别位于对应插设部的两侧。所述直插式芯片焊座用于焊接待组装直插式芯片相邻两只插脚的两个焊盘分布于对应插设部的两侧。如此，可增大焊盘间距，避免焊盘焊接插脚时发生端接现象，造成插脚短路。另外，本发明还提供一种采用所述直插式芯片焊座的直插式芯片组装结构。

    HIGH IMPEDANCE ELECTRICAL CONNECTION VIA
    26.
    发明申请
    HIGH IMPEDANCE ELECTRICAL CONNECTION VIA 审中-公开
    高阻抗电气连接

    公开(公告)号：WO2011053396A1

    公开(公告)日：2011-05-05

    申请号：PCT/US2010/042129

    申请日：2010-07-15

    Applicant: XILINX, INC.

    Inventor： WYLAND, Christopher, P.

    IPC: H01L23/66

    CPC classification number: H01L23/66 ,  H01L23/64 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09463 ,  H05K2201/09781 ,  H05K2201/09809 ,  H01L2924/00

    Abstract: Vias (106) are typically of a lower impedance than the signal lines (102, 128) connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. An embodiment avoids impedance mismatch in circuits and achieves an advance in the art by providing a via (106) with higher impedance through the addition of split ring resonators (104, 112, 120, 126) to each end of the via (106).

    Abstract translation: 通道（106）通常具有比连接到它们的信号线（102,128）更低的阻抗。 导致阻抗失配的噪声和反射信号可能要求电路以远低于所需的频率运行。 一个实施例避免了电路中的阻抗不匹配，并且通过向通孔（106）的每个端部添加开环谐振器（104,112,120,126）提供具有更高阻抗的通孔（106）来实现本领域的进步。

    Printed wiring board
    29.
    发明公开
    Printed wiring board 审中-公开
    Leiterplatte

    公开(公告)号：EP1983809A2

    公开(公告)日：2008-10-22

    申请号：EP08007057.6

    申请日：2008-04-09

    Applicant: YAZAKI CORPORATION

    Inventor： Masaoki, Yoshida ,  Nakayama, Takuya ,  Ueyama, Koji

    IPC: H05K1/11

    CPC classification number: H05K1/116 ,  H05K1/0256 ,  H05K3/3447 ,  H05K2201/09363 ,  H05K2201/09463 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/10651 ,  H05K2203/1446

    Abstract: The present invention is to provide a printed wiring board which can certainly prevent damage of conductive pattern caused by the terminal. The printed wiring board has a board, a conductive pattern, a through-hole and a non-conductive area. A lead wire of resistance mounted on the printed wiring board is inserted into the through-hole 4. The lead wire projects from a surface of the board, and is bent close to the surface. The non-conductive area is formed into a fan-shaped shape enlarging toward a tip of the lead wire from a center of the through-hole. Since the bent lead wire is arranged on the non-conductive area, the non-conductive area can prevent damage of the conductive pattern which is caused by touching the lead wire to the conductive pattern.

    Abstract translation: 本发明提供一种可以防止由端子引起的导电图案的损坏的印刷电路板。 印刷电路板具有基板，导电图案，通孔和非导电区域。 安装在印刷电路板上的电阻引线插入到通孔4中。引线从板的表面突出并且靠近表面弯曲。 非导电区域从通孔的中心形成为朝向引线的尖端扩大的扇形形状。 由于弯曲的引线布置在非导电区域上，所以非导电区域可以防止由引线接触导电图案而导致的导电图案的损坏。

    Printed wiring board, semiconductor package, and printed circuit board
    30.
    发明专利
    Printed wiring board, semiconductor package, and printed circuit board 有权
    印刷电路板，半导体封装和印刷电路板

    公开(公告)号：JP2013225610A

    公开(公告)日：2013-10-31

    申请号：JP2012097572

    申请日：2012-04-23

    Applicant: Canon Inc ,  キヤノン株式会社

    Inventor： HAYASHI YASUJI ,  KONDO TAKUYA ,  MATSUMOTO SHOJI

    IPC: H01L23/12

    CPC classification number: H05K1/0216 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/48227 ,  H05K1/0228 ,  H05K1/0242 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/114 ,  H05K1/116 ,  H05K1/14 ,  H05K1/141 ,  H05K1/162 ,  H05K1/18 ,  H05K2201/0939 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09463 ,  H05K2201/09636 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734

    Abstract: PROBLEM TO BE SOLVED: To reduce crosstalk noise occurring between signal wiring lines.SOLUTION: In a first conductor layer 101, first and second signal wiring patterns 111 and 112 are formed. In a second conductor layer 102 that is a surface layer, a first pad 121 electrically connected to the first signal wiring pattern 111 through the first via 131 and a second pad 122 electrically connected to the second signal wiring pattern 112 through a second via 132 are formed. A third conductor layer 103 is disposed between the first conductor layer 101 and the second conductor layer 102, and an insulator 105 is interposed among the conductor layers. In the third conductor layer 103, a first via pad 141 electrically connected to the first via 131 is formed. The first via pad 141 is overlapped with the second pad 122 as viewed from a direction perpendicular to a substrate surface 100a, and has a facing portion 141a that faces the second pad 122 via the insulator 105.

    Abstract translation: 要解决的问题：减少信号布线之间发生的串扰噪声。解决方案：在第一导体层101中，形成第一和第二信号布线图案111和112。 在作为表面层的第二导体层102中，通过第一通孔131电连接到第一信号布线图案111的第一焊盘121和通过第二通孔132电连接到第二信号布线图案112的第二焊盘122， 形成。 第三导体层103设置在第一导体层101和第二导体层102之间，绝缘体105插入在导体层之间。 在第三导体层103中，形成与第一通孔131电连接的第一通孔焊盘141。 当从垂直于基板表面100a的方向观察时，第一通孔焊盘141与第二焊盘122重叠，并且具有经由绝缘体105面对第二焊盘122的对置部分141a。

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