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公开(公告)号：KR1019930008579B1
公开(公告)日：1993-09-09
申请号：KR1019900004604
申请日：1990-04-03
Applicant: 한국전자통신연구원
IPC: H01L27/108
Abstract: The method for increasing the capacitor surface comprises steps: (a) forming a transistor on a silicon substrate; (b) forming a polycide layer, depositing a LTO, etching the defined bit line region, and forming an oxide layer spacer to form a bit line; (c) forming a storage electrode contact region by forming a silicon nitride, and a 1st silicon oxide layers; (d) forming a 1st polysilicon, 2nd silicon oxide, a 2nd polysilicon, and a 3rd silicon oxide layers in sequence; (e) etching them after defining the column type isolation region; (f) connecting a 1st and 2nd polysilicon with the polysilicon spacer; (g) forming the storage electrode by removing the 1st and 3rd silicon oxide layers; and (h) forming the plate electrode by forming the capacitor dielectric layer to ONO structure.
Abstract translation: 增加电容器表面的方法包括以下步骤：（a）在硅衬底上形成晶体管; （b）形成多晶硅化物层，沉积LTO，蚀刻所定义的位线区域，以及形成氧化物层间隔物以形成位线; （c）通过形成氮化硅和第一氧化硅层形成存储电极接触区; （d）依次形成第一多晶硅，第二氧化硅，第二多晶硅和第三氧化硅层; （e）在定义柱型隔离区之后蚀刻它们; （f）将第一和第二多晶硅与多晶硅间隔物连接; （g）通过去除第一和第三氧化硅层形成存储电极; 和（h）通过将电容器介电层形成ONO结构来形成平板电极。
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公开(公告)号：KR1020160149361A
公开(公告)日：2016-12-28
申请号：KR1020150086013
申请日：2015-06-17
Applicant: 한국전자통신연구원
CPC classification number: H03K5/135 , H03K2005/00052 , H03L7/081 , H03L2207/50
Abstract: 본발명에따른기준클록신호에대응하여출력클록신호를생성하는위상고정루프는, 상기출력클록신호로부터제 1 시간지연을가지는제 1 인터폴레이터클록신호를생성하는제 1 위상인터폴레이터, 상기출력클록신호로부터제 2 시간지연을가지는제 2 인터폴레이터클록신호를생성하는제 2 위상인터폴레이터, 상기제 1 및제 2 인터폴레이터클록신호들중 하나를소정의비율로선택하도록제어하는인터폴레이터제어신호를생성하는인터폴레이터제어기, 상기인터폴레이터제어신호에따라상기제 1 및제 2 인터폴레이터클록신호들중 하나를선택하는멀티플렉서, 상기제 1 및제 2 인터폴레이터클록신호들중 선택된하나를분주하여분주클록신호를생성하는분주기, 그리고상기기준클록신호및 상기분주클록신호사이의위상차이에대응하여상기출력클록신호의주파수를제어하는디지털제어발진기를포함한다.
Abstract translation: 提供了一种产生对应于参考时钟信号的输出时钟信号的锁相环（PLL），PLL包括第一相位内插器，其被配置为产生具有来自输出时钟信号的第一时间延迟的第一内插时钟信号，以及 第二相位插值器被配置为产生具有来自输出时钟信号的第二时间延迟的第二内插时钟信号。 基于多路复用第一内插时钟信号和第二内插时钟信号，PLL控制输出时钟信号的频率。
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公开(公告)号：KR1020160142652A
公开(公告)日：2016-12-13
申请号：KR1020150078658
申请日：2015-06-03
Applicant: 한국전자통신연구원
IPC: H04B1/10
Abstract: 본발명의일 실시예에따른간섭신호제거장치는입력신호를수신하는안테나, 입력신호를제1 신호및 제2 신호로분배하는증폭부, 제1 신호의대상주파수영역의신호에대한위상을미리지정된수치만큼변화시키는제1 위상변환기, 제2 신호의대상주파수영역의신호에대한위상을미리지정된수치만큼변화시키는제2 위상변환기, 제1 신호와제2 신호의지연시간이동일하도록및 상기제2 신호중 하나이상을보정하는타이밍제어기; 및위상이변화된제1 신호및 제2 신호에대한차분신호를생성하는뺄셈부를포함한다.
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公开(公告)号：KR101682652B1
公开(公告)日：2016-12-06
申请号：KR1020130060190
申请日：2013-05-28
Applicant: 한국전자통신연구원
CPC classification number: G01S13/103 , G01S7/28 , G01S13/0209
Abstract: 높은해상도를갖는펄스레이더장치를제시한다. 제시된장치는송신펄스반복주기를갖는송신트리거신호를근거로펄스를발생시켜송신안테나를통해목표물에게로송신하는펄스발생부, 외부로부터의클록을이용하여송신트리거신호를생성하여펄스발생부에게로제공하고외부로부터의클록을이용하여송신펄스반복주기와는시간차이나는다수의클록신호를발생시키는동기화부, 및외부로부터의선택신호에근거하여다수의클록신호에서어느한 클록신호를선택하여수신기의샘플러의샘플링클록으로제공하는스위치부를포함한다.
Abstract translation: 公开了一种脉冲雷达装置。 脉冲雷达装置包括脉冲发生单元，接收单元，同步单元和开关单元。 脉冲发生单元基于具有发送脉冲重复周期的发送触发信号产生脉冲，并且经由发送天线将脉冲发送到目标。 同步单元使用外部参考时钟生成发送触发信号，向脉冲发生单元提供发送触发信号，并且使用外部参考时钟产生相对于发送脉冲触发信号具有时间延迟的多个时钟信号。 开关单元响应于外部选择信号从多个时钟信号中选择一个时钟信号，并将所选择的时钟信号提供给采用具有提供的采样时钟的采样器的接收器单元。
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Patent Agency Ranking
公开(公告)号：KR1020150108147A
公开(公告)日：2015-09-25
申请号：KR1020140030970
申请日：2014-03-17
Applicant: 한국전자통신연구원
Abstract: 본 발명은 안테나와 송수신 칩 및 디지털 신호처리 칩을 하나의 패키지로 소형화, 집적화, 경량화하기 위해 단일 기판 위에 안테나와 레이더 온 칩으로 패키징하는 밀리미터파용 레이더 온 패키지에 관한 것으로, 밀리미터파용 레이더 온 패키지는, 다층 기판; 상기 다층 기판의 일면에 배치되는 RFIC 송신 모듈과 RFIC 수신 모듈로 구성되는 RFIC 칩; 및 상기 다층 기판의 타면에 형성되어 안테나 송신부와 안테나 수신부를 구성하며, 유전체 공진기 안테나의 노출 영역인 다수의 멀티 어레이 안테나를 포함한다.
Abstract translation: 本发明涉及一种用于毫米波的雷达，其能够在单个基板上封装天线和雷达，用于将天线，发射和接收芯片以及数字信号处理芯片小型化，集成和照明，以便将其作为 一包 用于毫米波的包装雷达包括：多层基板; RFIC芯片，其由布置在所述多层基板的一侧上的RFIC传输模块和RFIC接收模块构成; 并且形成在多层基板的另一侧上的多个多阵列天线包括天线发送单元和天线接收单元，并且是介质谐振器天线的曝光区域。
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公开(公告)号：KR1020120116335A
公开(公告)日：2012-10-22
申请号：KR1020120026571
申请日：2012-03-15
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A radar device is provided to improve the reliability of measurement by using a digital modulation-demodulation technology. CONSTITUTION: A transmitting unit(110) converts a digital modulation signal generated by a digital signal processing unit(130) into a carrier frequency through analog conversion. The transmitting unit transmits a generated transmission signal(T1) through a transmission antenna(141). A receiving unit(120) receives an echo signal(R1) reflected from a target(150) and performs digital conversion to the same. The digital signal processing unit demodulates the each signal. [Reference numerals] (130) Digital signal processing unit; (AA) Digital code
Abstract translation: 目的：提供雷达装置，通过数字调制解调技术提高测量的可靠性。 构成：发送单元（110）通过模拟转换将由数字信号处理单元（130）产生的数字调制信号转换为载波频率。 发送单元通过发送天线（141）发送生成的发送信号（T1）。 接收单元（120）接收从目标（150）反射的回波信号（R1），并对其进行数字转换。 数字信号处理单元解调每个信号。 （附图标记）（130）数字信号处理单元; （AA）数字代码
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公开(公告)号：KR1020100062806A
公开(公告)日：2010-06-10
申请号：KR1020090023897
申请日：2009-03-20
Applicant: 한국전자통신연구원
CPC classification number: H03L7/1075 , H03L7/085 , H03L7/093 , H03L7/1976
Abstract: PURPOSE: A frequency adjustment loop is provided to form a lock state of the frequency adjustment loop within fast time by moving an output frequency of an oscillator to wanting frequency band. CONSTITUTION: An oscillator(140) controls an output frequency according to inputted control bit. A programmable divider(150) divides the output frequency of the oscillator according to varied dividing ratio. A counter unit(110) is inputted an output signal of the programmable divider and a reference frequency. The counter unit measures a clock number of the output signal of the divider in one period of the reference frequency. A frequency detector(120) outputs the value tacking out from the clock number outputted from the counter unit in a standard comparison value to a control bit of the oscillator. The programmable divider decides the divide ratio about the output signal of the oscillator by receiving a feedback the clock number outputted from the counter unit.
Abstract translation: 目的：通过将振荡器的输出频率移动到想要的频带，提供频率调整回路以在快速时间内形成频率调节回路的锁定状态。 构成：振荡器（140）根据输入的控制位控制输出频率。 可编程分频器（150）根据分频比分频振荡器的输出频率。 计数器单元（110）输入可编程分频器的输出信号和参考频率。 计数器单元在参考频率的一个周期内测量分频器的输出信号的时钟数。 频率检测器（120）将从标准比较值中的从计数器单元输出的时钟编号输出的值输出到振荡器的控制位。 可编程分频器通过从计数器单元输出的时钟数字接收反馈来决定关于振荡器输出信号的分频比。
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公开(公告)号：KR100793318B1
公开(公告)日：2008-01-11
申请号：KR1020060096350
申请日：2006-09-29
Applicant: 한국전자통신연구원
Abstract: A charge pump circuit having a digital leakage current canceling circuit and a tuning circuit comprising the charge pump circuit are provided to prevent the degradation of jitter and noise performance of a system using the charge pump circuit, by removing a leakage current of the charge pump circuit by compensating for the leakage current digitally. A charge pump comprises a pumping PMOS transistor(411) and a pumping NMOS transistor(412). A compensation transistor array(430) comprises more than two compensation transistors generating a compensation current to cancel a leakage current generated in the charge pump. A switch array(420) switches the connection of each compensation transistor, according to a digital control code applied from the outside.
Abstract translation: 提供具有数字泄漏电流消除电路的电荷泵电路和包括电荷泵电路的调谐电路，以通过去除电荷泵电路的漏电流来防止使用电荷泵电路的系统的抖动和噪声性能的劣化 通过数字补偿泄漏电流。 电荷泵包括泵浦PMOS晶体管（411）和泵浦NMOS晶体管（412）。 补偿晶体管阵列（430）包括多于两个补偿晶体管，产生补偿电流以消除在电荷泵中产生的漏电流。 根据从外部施加的数字控制码，开关阵列（420）切换每个补偿晶体管的连接。
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公开(公告)号：KR100731544B1
公开(公告)日：2007-06-22
申请号：KR1020060033587
申请日：2006-04-13
Applicant: 한국전자통신연구원
IPC: H01L21/3205
Abstract: A multi-layer wiring coplanar waveguide is provided to minimize the loss of a coplanar waveguide and to maximize slow-wave effect by using an intermediate metal layer having a width less than that of a ground. An uppermost metal layer is designed with a ground(41)-signal(40)-ground(41). An intermediate layer(43) has a structure for maximizing volume where an electromagnetic wave propagates. A lowermost metal layer is used as a shield layer and connected through the ground of the uppermost metal layer, the intermediate layer, and the via-hole. The intermediate layer is comprised of a plurality of intermediate metal layers located at a lower of the ground of the uppermost metal layer. The intermediate metal layers have a width less than that of the ground.
Abstract translation: 提供多层布线共面波导以最小化共面波导的损耗并且通过使用宽度小于地面宽度的中间金属层来最大化慢波效应。 最上面的金属层设计为具有地面（41） - 信号（40） - 地面（41）。 中间层（43）具有用于使电磁波传播的体积最大化的结构。 最下面的金属层用作屏蔽层，并通过最上面的金属层，中间层和通孔的接地连接。 中间层由位于最上层金属层的地面下部的多个中间金属层构成。 中间金属层的宽度小于地面的宽度。
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