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    INTEGRATED CIRCUIT DEVICE WITH DEEP TRENCH ISOLATION REGIONS FOR ALL INTER-WELL AND INTRA-WELL ISOLATION AND WITH A SHARED CONTACT TO A JUNCTION BETWEEN ADJACENT DEVICE DIFFUSION REGIONS AND AN UNDERLYING FLOATING WELL SECTION
    31.
    发明专利
    INTEGRATED CIRCUIT DEVICE WITH DEEP TRENCH ISOLATION REGIONS FOR ALL INTER-WELL AND INTRA-WELL ISOLATION AND WITH A SHARED CONTACT TO A JUNCTION BETWEEN ADJACENT DEVICE DIFFUSION REGIONS AND AN UNDERLYING FLOATING WELL SECTION 未知

    公开(公告)号：CA2757776A1

    公开(公告)日：2010-12-02

    申请号：CA2757776

    申请日：2010-05-04

    Applicant: IBM

    Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

    IPC: H01L21/8244 ,  H01L27/11

    Abstract: Disclosed are embodiments of an improved integrated circuit device structure (200) (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) (121a and 121b) and a method of forming the structure that uses DTI regions (160) for all inter- well and intra- well isolation and, thereby provides a low-cost isolation scheme that avoids FET width variations due to STI-DTI misalignment. Furthermore, because the DTI regions (160) used for intra- well isolation effectively create some floating well sections, (203) which must each be connected to a supply voltage (e.g., Vdd) (280) to prevent threshold voltage (Vt) variations, the disclosed integrated circuit device also includes a shared contact (280) to a junction between the diffusion regions (221 and 222) of adjacent devices (121a and 121b) and an underlying floating well section (205). This shared contact (280) eliminates the cost and area penalties that would be incurred if a discrete supply voltage contact was required for each floating well section (205).

    32.
    发明专利
    未知

    公开(公告)号：DE10296953B4

    公开(公告)日：2010-04-08

    申请号：DE10296953

    申请日：2002-06-06

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

    IPC: H01L21/283 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

    Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

    Asymmetrischer Anti-Halo-Feldeffekttransistor und Verfahren zu seiner Herstellung
    35.
    发明专利
    Asymmetrischer Anti-Halo-Feldeffekttransistor und Verfahren zu seiner Herstellung 未知

    公开(公告)号：DE102012222265B4

    公开(公告)日：2015-06-25

    申请号：DE102012222265

    申请日：2012-12-05

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  ADKISSON JAMES W

    IPC: H01L21/336 ,  H01L21/266 ,  H01L29/78

    Abstract: Verfahren zum Ausbilden einer integrierten Schaltungsstruktur, wobei das Verfahren aufweist: Implantieren einer ersten Kompensationsimplantation in ein Substrat, die sich bis zu einer zweiten Tiefe in das Substrat erstreckt; Strukturieren einer Maske auf der ersten Kompensationsimplantation in dem Substrat, wobei die Maske eine Öffnung beinhaltet, die eine Kanalposition des Substrats freilegt; Implantieren einer zweiten Kompensationsimplantation in die Kanalposition des Substrats durch die Öffnung in einem Winkel, der von der Senkrechten zu einer oberen Fläche des Substrats versetzt ist, wobei die zweite Kompensationsimplantation im Verhältnis zu einer gegenüberliegenden zweiten Seite der Kanalposition näher an einer ersten Seite der Kanalposition positioniert ist und die zweite Kompensationsimplantation ein Material aufweist, das dieselbe Dotierungspolarität wie eine Halbleiter-Kanalimplantation aufweist, die sich bis zu einer ersten Tiefe in ein Substrat erstreckt, wobei die erste Tiefe im Verhältnis zu der zweiten Tiefe weiter von einer oberen Fläche des Substrats entfernt ist, wobei die erste Kompensationsimplantation ein Material aufweist, das eine andere Dotierungspolarität als die Halbleiter-Kanalimplantation aufweist; Ausbilden eines Gate-Leiters über der Kanalposition des Substrats in der Öffnung der Maske; Entfernen der Maske, sodass der Gate-Leiter auf der Kanalposition des Substrats stehend zurückbleibt; und Implantieren von Source- und Drain-Implantationen in Source/Drain-Bereiche des Substrats, die an die Kanalposition angrenzen.

    FinFET device formed using a sacrificial Silicon-Germanium alloy layer
    36.
    发明专利
    FinFET device formed using a sacrificial Silicon-Germanium alloy layer 未知

    公开(公告)号：GB2503806A

    公开(公告)日：2014-01-08

    申请号：GB201311356

    申请日：2013-01-28

    Applicant: IBM

    Inventor： NOWAK EDWARD J ,  ANDERSON BRENT ALAN ,  BRYANT ANDRES

    IPC: H01L29/66 ,  H01L29/78

    Abstract: A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region 154 and source/drain (S/D) regions 156, formed on each end of the channel region 154, where an entire bottom surface of the channel region 154 contacts a top surface of a first lower insulator 922 and bottom surfaces of the S/D regions 156 contact top surfaces of a second lower insulator layer 1224; the FinFET structure also includes extrinsic S/D regions 1056 that contact a top surface and both side surfaces of each of the S/D regions 156 and top surfaces of the second lower insulator layer 1224; the FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region 154, that is disposed above the first lower insulator 722 and not above second lower insulator layer 1224, in which the gate stack is electrically insulated from the extrinsic S/D regions 1056 by the conformal dielectric. In the disclosed method a silicon-germanium alloy layer is provided beneath the channel region 154 initially, then replaced with the first 722 and second 1224 lower insulators following deposition of the sacrificial gate and removal of the sacrificial gate, respectively.

    SELF-ALIGNED DYNAMIC THRESHOLD CMOS DEVICE
    37.
    发明专利
    SELF-ALIGNED DYNAMIC THRESHOLD CMOS DEVICE 未知

    公开(公告)号：MY123211A

    公开(公告)日：2006-05-31

    申请号：MYPI9903850

    申请日：1999-09-06

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  NOWAK EDWARD J

    IPC: H01L21/36 ,  H01L29/78 ,  H01L21/336 ,  H01L29/786

    Abstract: A METHOD OF MAKING A SELF-ALIGNED DYNAMIC THRESHOLD FIELD DEVICE HAVING A DYNAMIC THRESHOLD VOLTAGE INCLUDES DEPOSITING A MANDREL LAYER (32) ON THE SURFACE OF AN SO&Igr; SUBSTRATE (12), THEN ETCHING A GATE OPENING (34) IN THE MANDREL LAYER. THE GATE OPENING IS NARROWED BY DEPOSITING SPACER MATERIAL (38, 40, 44, 46) AND A HIGHLY DOPED REGION (42), FORMING A LOW RESISTANCE BODY REGION, IS CREATED BY ION IMPLANTATION. THE NARROWED GATE OPENING PREVENTS THE LOW RESISTANCE BODY FROM CONNECTING THE SOURCE/ DRAIN REGIONS TO BE FORMED ON OPPOSITE SIDES OF THE GATE STRUCTURE (14). A GATE IS FORMED BY DEPOSITING A DIELECTRIC LAYER (54) IN THE GATE OPENING, AND ADDING A LAYER OF GATE MATERIAL (56), THEN CHEMICAL-MECHANICAL POLISHING TO THE LEVEL OF THE MANDREL LAYER, THEN REMOVING THE MANDREL LAYER. CONVENTIONAL PROCESSING IS THEN USED TO CREATE SOURCE/DRAIN DIFFUSION REGIONS. THE GATE IS CONNECTED TO THE BODY BY CREATING A CONTACT REGION (16) AT ONE END OF THE GATE. THE INVENTION INCLUDES THE DEVICE MADE BY THE METHOD. THE DEVICE NEEDS LESS SURFACE AREA THAN PREVIOUS DEVICES OF THIS TYPE DUE TO THE LOW RESISTANCE BODY AND THE CONNECTION REGION LOCATED AT ONE END OF THE GATE STRUCTURE, AND THE METHOS SELF-ALIGNS THE GATE AND THE BODY REGION, WHILE ACCURATELY CONTROLLING THEIR RELATIVE SIZES.(FIGURE 1)

    39.
    发明专利
    未知

    公开(公告)号：DE69021284T2

    公开(公告)日：1996-04-18

    申请号：DE69021284

    申请日：1990-05-21

    Applicant: IBM

    Inventor： ARNETT PATRICK CLINTON ,  BRYANT ANDRES ,  FOSTER JOHN STUART ,  FROMMER JANE ELIZABETH ,  IWATA JON ASAO CARY

    IPC: G01Q60/00 ,  G03F1/00 ,  G03F7/20 ,  H01J37/317 ,  H01L21/027 ,  H01L21/30

    Abstract: A high resolution lithographic mask having a desired pattern is generated and used to replicate the pattern onto a film in a one-step process. A film of phase-changeable material in one state is provided on a conductive substrate. By scanning tunneling microscope techniques, the state and thereby the conductivity or other property of the material in selected areas (a min -c min ) of the film is changed to a second state to provide from the film a mask (19) having a desired pattern defined by crystalline areas. Amorphous material need not be removed from the mask. To replicate the pattern on another film (16), the latter is placed on another conductive substrate (17); the mask is positioned (21p-21r) with its patterned side within electron tunneling distance (19p-19r) of said other film; and the pattern is replicated in a single step by applying a voltage between the mask and other film. The voltage charge on said mask is positive and negative on said other film to cause current to flow in the crystalline areas of said mask and, by electron flow from said film to the mask, eliminate backscattering and insure high resolution. As the state changes (e.g., from crystalline to amorphous) in the pattern areas of said other film, conductivity in the crystalline areas will progressively decrease and, by causing a corresponding reduction in current flow in the crystalline areas, minimize the risk of undesired broadening of exposed areas of said other film.

    40.
    发明专利
    未知

    公开(公告)号：DE69021284D1

    公开(公告)日：1995-09-07

    申请号：DE69021284

    申请日：1990-05-21

    Applicant: IBM

    Inventor： ARNETT PATRICK CLINTON ,  BRYANT ANDRES ,  FOSTER JOHN STUART ,  FROMMER JANE ELIZABETH ,  IWATA JON ASAO CARY

    IPC: G01Q60/00 ,  G03F1/00 ,  G03F7/20 ,  H01J37/317 ,  H01L21/027 ,  H01L21/30

    Abstract: A high resolution lithographic mask having a desired pattern is generated and used to replicate the pattern onto a film in a one-step process. A film of phase-changeable material in one state is provided on a conductive substrate. By scanning tunneling microscope techniques, the state and thereby the conductivity or other property of the material in selected areas (a min -c min ) of the film is changed to a second state to provide from the film a mask (19) having a desired pattern defined by crystalline areas. Amorphous material need not be removed from the mask. To replicate the pattern on another film (16), the latter is placed on another conductive substrate (17); the mask is positioned (21p-21r) with its patterned side within electron tunneling distance (19p-19r) of said other film; and the pattern is replicated in a single step by applying a voltage between the mask and other film. The voltage charge on said mask is positive and negative on said other film to cause current to flow in the crystalline areas of said mask and, by electron flow from said film to the mask, eliminate backscattering and insure high resolution. As the state changes (e.g., from crystalline to amorphous) in the pattern areas of said other film, conductivity in the crystalline areas will progressively decrease and, by causing a corresponding reduction in current flow in the crystalline areas, minimize the risk of undesired broadening of exposed areas of said other film.

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