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    31.
    发明专利
    未知

    公开(公告)号：DE10134089A1

    公开(公告)日：2003-01-30

    申请号：DE10134089

    申请日：2001-07-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SECK MARTIN ,  TILKE ARMIN ,  KRIZ JAKOB

    IPC: H01L21/225 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737

    Abstract: The invention relates to a method for producing a bipolar transistor comprising a polysilicon emitter, according to which a collector region of a first conductivity type and an adjacent base region of a second conductivity type are created. At least one layer consisting of an insulating material is then applied, said layer or layers being structured in such a way that at least one section of the base region is exposed. A layer consisting of a polycrystalline semiconductor material of the first conductivity type, which is highly doped with doping atoms, is subsequently created, in such a way that the exposed section is essentially covered. A second layer consisting of a highly conductive material is then created on the layer consisting of the polycrystalline semiconductor material, forming a dual-layer emitter with the latter. At least one portion of the doping atoms of the first conductivity type of the highly doped polycrystalline semiconductor layer is then caused to diffuse into the base region, to create an emitter region of the first conductivity type.

    Verfahren zum Herstellen einer elektronischen Komponente
    33.
    发明专利
    Verfahren zum Herstellen einer elektronischen Komponente 未知

    公开(公告)号：DE102013112817B4

    公开(公告)日：2020-03-12

    申请号：DE102013112817

    申请日：2013-11-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TRICHY RENGARAJAN GOPALAKRISHNAN ,  TILKE ARMIN

    IPC: H01L21/784 ,  H01L21/283 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78

    Abstract: Verfahren, welches folgende Schritte umfasst:Bereitstellen eines Halbleiter-Wafers (10), der eine erste Hauptfläche (10.1) und eine der ersten Hauptfläche (10.1) entgegengesetzte zweite Hauptfläche (10.2) und mehrere Halbleiterchipgebiete (10A) umfasst,Aufbringen einer ersten Materialschicht (15) auf die erste Hauptfläche (10.1) des Halbleiter-Wafers (10),Anbringen eines ersten Trägers (20) an der ersten Materialschicht (15),Zerlegen des Halbleiter-Wafers (10) und der ersten Materialschicht (15) entlang Zerlegungsbahnen (10B), welche die Halbleiterchipgebiete (10A) umgeben, undAbscheiden einer zweiten Materialschicht (40) in durch das Zerlegen des Halbleiter-Wafers (10) und der ersten Materialschicht (15) erhaltenen Zerlegungsgräben (30), wobei die erste und die zweite Materialschicht (15, 40) unterschiedliche Löslichkeitsparameter haben.

    36.
    发明专利
    未知

    公开(公告)号：DE102006036797A1

    公开(公告)日：2007-03-29

    申请号：DE102006036797

    申请日：2006-08-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BECK MICHAEL ,  KIM HONG BEE ,  TILKE ARMIN ,  WENDT HERMANN

    IPC: H01L21/768

    Abstract: In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.

    38.
    发明专利
    未知

    公开(公告)号：DE102004021240A1

    公开(公告)日：2005-11-17

    申请号：DE102004021240

    申请日：2004-04-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TILKE ARMIN ,  WAGNER CAJETAN ,  ROCHEL MARKUS

    IPC: H01L21/8249 ,  H01L29/737

    Abstract: Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed for the purpose of carrying out a first collector implantation for the purpose of forming a collector connection zone. After the formation of a hard mask layer and a first etching mask, the hard mask layer is patterned and an emitter window is uncovered using the patterned hard mask layer. Using the patterned hard mask layer a second collector implantation is effected for the purpose of forming a collector zone, a base layer being formed in the region of the emitter window. Afterward, using a second etching mask, a field effect transistor region is uncovered and the patterned hard mask layer is removed in this region in order finally to form a second electrically conductive layer over the whole area for the purpose of realizing an emitter layer and a second split gate layer. Both the bipolar transistor and the field effect transistor are subsequently completed in a customary manner, in particular a source/drain implantation being used simultaneously for the doping of the emitter layer. Since the gate is deposited in two layers, the first layer simultaneously serving as base connection layer and the second layer simultaneously serving as emitter layer, up to two lithography planes can be obviated and costs can thereby be saved.

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