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41.发明授权
公开(公告)号：KR101419524B1
公开(公告)日：2014-07-14
申请号：KR1020120153420
申请日：2012-12-26
Applicant: (재)한국나노기술원
Abstract: 본 발명은 반도체 발광 다이오드 소자에 있어서, 반도체 발광 다이오드 소자의 제조 방법에 있어서, 기판 상층에 레지스트층을 형성하는 제1단계와, 상기 레지스트층을 패터닝하여 3차원 블락킹(blocking) 마스크를 형성하는 제2단계, 상기 3차원 블락킹 마스크 상층 및 기판 상층에 블락킹 패턴층을 증착하는 제3단계, 상기 3차원 블락킹 마스크를 제거하여 기판 상층에 "┰" 형태의 3차원 블락킹 패턴을 형성하는 제4단계 및 상기 3차원 블락킹 패턴 형성 후 반도체층을 증착하는 제5단계를 포함하여 이루어지는 것을 특징으로 하는 3차원 블락킹 패턴을 이용한 반도체 발광 다이오드 소자의 제조 방법 및 이에 의해 제조된 반도체 발광 다이오드 소자를 기술적 요지로 한다. 이에 의해 기판 상에 3차원 블락킹 패턴을 형성하여 반도체층 형성시 발생하는 결함을 줄여서 발광 다이오드 소자의 효율을 개선시키는 이점이 있다.
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42.发明公开스텝형 3차원 블락킹 패턴을 이용한 반도체 발광 다이오드 소자의 제조 방법 및 이에 의해 제조된 반도체 발광 다이오드 소자 有权使用步骤类型3-D阻挡图案和发光二极管的发光二极管的制造方法
公开(公告)号：KR1020140083537A
公开(公告)日：2014-07-04
申请号：KR1020120153425
申请日：2012-12-26
Applicant: (재)한국나노기술원
CPC classification number: H01L33/0079 , H01L21/0274 , H01L33/22 , H01L33/32
Abstract: A technological subject matter of the present invention is to provide a method of fabricating a semiconductor light emitting diode device using a step type 3-D blocking pattern and a light emitting diode device fabricated by the same. The method of fabricating the semiconductor light emitting diode device in terms of the semiconductor light emitting diode device includes a first step of forming a first resist layer on a top of a substrate; a second step of forming a first blocking mask by patterning the first resist layer; a third step of depositing a first blocking pattern layer on the first blocking mask; a fourth step of forming a 3-D first blocking pattern in a ″T″ shape on a top of the substrate by removing the first blocking mask; a fifth step of forming a second resist layer after the first blocking layer is patterned; a sixth step of forming a second blocking mask by patterning the second resist layer; a seventh step of depositing a second blocking pattern layer on top of the second blocking mask; a eighth step of forming a 3-D second blocking pattern in a ″T″ shape having an upper region entirely covering a region between the first blocking patterns, and formed in a step type on a region between the first blocking patterns on the substrate by removing the second blocking mask; and a nineth step of depositing a semiconductor layer after the second blocking pattern is formed. Thus, the present invention has an advantage of improving efficiency of the light emitting diode device by reducing defects occurring when forming the semiconductor layer through by the 3-D blocking pattern on the top of the substrate.
Abstract translation: 本发明的技术主题是提供一种制造使用阶梯型3-D阻挡图案的半导体发光二极管器件的方法和由其制造的发光二极管器件。 关于半导体发光二极管器件制造半导体发光二极管器件的方法包括：在衬底的顶部上形成第一抗蚀剂层的第一步骤; 通过图案化第一抗蚀剂层形成第一阻挡掩模的第二步骤; 第三步骤，在所述第一阻挡掩模上沉积第一阻挡图案层; 通过去除第一阻挡掩模在衬底的顶部上形成“T”形的3-D第一阻挡图案的第四步骤; 在第一阻挡层被图案化之后形成第二抗蚀剂层的第五步骤; 通过图案化第二抗蚀剂层形成第二阻挡掩模的第六步骤; 在所述第二阻挡掩模的顶部上沉积第二阻挡图案层的第七步骤; 形成“T”形的三维第二阻挡图案的第八步骤，其具有完全覆盖第一阻挡图案之间的区域的上部区域，并且在基板上的第一阻挡图案之间的区域上以阶梯型形成， 去除第二阻挡掩模; 以及在形成第二阻挡图案之后沉积半导体层的第九步骤。 因此，本发明具有通过减少在通过基板顶部的3-D阻挡图案形成半导体层时发生的缺陷来提高发光二极管器件的效率的优点。
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公开(公告)号：KR1020130079828A
公开(公告)日：2013-07-11
申请号：KR1020120000560
申请日：2012-01-03
Applicant: (재)한국나노기술원
IPC: H01L31/06 , H01L31/0236 , H01L31/042 , H01L33/22
Abstract: PURPOSE: An optoelectronic device including a nano-grayscale pattern and a manufacturing method thereof are provided to improve electrical conductivity and photoelectric conversion efficiency by forming an active layer with an uneven or curved shape to increase a surface area. CONSTITUTION: A semiconductor layer (102) is formed on a conductive substrate (101). An n-type semiconductor layer (103) with an uneven or curved structure is formed on the semiconductor layer. An active layer (104) with the uneven or curved structure is formed on the n-type semiconductor layer. The active layer has one or more structures among a spherical structure, a tubal structure, a circular pillar structure, a polygonal pillar structure, a pyramidal structure, a one-dimensional structure, a two-dimensional structure, and a three-dimensional structure. A p-type semiconductor layer (105) is formed on the active layer.
Abstract translation: 目的：提供一种包括纳米灰度图案及其制造方法的光电子器件，通过形成具有不平坦或弯曲形状的活性层以增加表面积来提高导电性和光电转换效率。 构成：在导电基板（101）上形成半导体层（102）。 在半导体层上形成具有不均匀或弯曲结构的n型半导体层（103）。 在n型半导体层上形成具有凹凸或弯曲结构的有源层（104）。 活性层在球形结构，输卵管结构，圆柱结构，多边形柱状结构，锥体结构，一维结构，二维结构和三维结构中具有一种或多种结构。 在有源层上形成p型半导体层（105）。
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公开(公告)号：KR1020120087491A
公开(公告)日：2012-08-07
申请号：KR1020110008715
申请日：2011-01-28
Applicant: (재)한국나노기술원
IPC: H01L51/42
CPC classification number: Y02E10/549 , Y02P70/521 , H01L51/42
Abstract: PURPOSE: An organic solar cell and a fabricating method thereof are provided to improve energy conversion efficiency by increasing an interfacial area of an electro donor layer and an electron accepting layer. CONSTITUTION: An electron accepting layer(130) is formed on a anode(120). A regular pattern is formed on an upper side of the electron accepting layer. The pattern consists of two cross sections. An electro donor layer(140) is formed on the electron accepting layer. A cathode(150) is formed on the electro donor layer.
Abstract translation: 目的：提供有机太阳能电池及其制造方法，以通过增加电供体层和电子接受层的界面面积来提高能量转换效率。 构成：在阳极（120）上形成电子接受层（130）。 在电子接受层的上侧形成规则图案。 图案由两个横截面组成。 电子给体层（140）形成在电子接受层上。 在电供体层上形成阴极（150）。
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公开(公告)号：KR1020120022207A
公开(公告)日：2012-03-12
申请号：KR1020100085509
申请日：2010-09-01
Applicant: (재)한국나노기술원
IPC: H01L33/22
CPC classification number: H01L33/0079 , H01L21/268 , H01L2933/0083
Abstract: PURPOSE: A semiconductor light emitting device including a patterned semiconductor layer and a manufacturing method thereof are provided to improve the efficiency of the semiconductor light emitting device by decreasing laser to an active layer in a laser lift off. CONSTITUTION: A p type electrode(135) is formed on a conductive substrate. A p type semiconductor layer, an active layer(120), and an n type semiconductor layer are successively laminated on the p type electrode. An n type electrode(145) is formed on an n type semiconductor layer. A concave part of a nano meter photonic crystal pattern is regularly formed on the surface of the n type semiconductor layer.
Abstract translation: 目的：提供包括图案化半导体层的半导体发光器件及其制造方法，以通过在激光剥离中将有源层激光降低而提高半导体发光器件的效率。 构成：在导电性基板上形成p型电极（135）。 在p型电极上依次层叠p型半导体层，有源层（120）和n型半导体层。 n型电极（145）形成在n型半导体层上。 在n型半导体层的表面上规则地形成纳米级光子晶体图案的凹部。
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Patent Agency Ranking
公开(公告)号：KR1020110136340A
公开(公告)日：2011-12-21
申请号：KR1020100056267
申请日：2010-06-15
Applicant: (재)한국나노기술원
CPC classification number: C01B32/184 , B29C33/38 , B81C1/0046 , B82B3/00 , C01B2204/04 , G03F7/0002
Abstract: PURPOSE: A method for forming a graphene pattern using an imprinting technique is provided to easily adjust the thickness of transferred graphene by adjusting the strength of a voltage if a graphene transferring process is implemented based on an electronic filed. CONSTITUTION: An imprint stamp(210), in which a pattern(205) is formed on a master substrate(200), is prepared. A metal film(220) containing a graphitization catalyst is formed on the imprint stamp. Graphene(230) is formed on the imprint stamp. The graphene is transferred to a substrate(240) for manufacturing devices in order to form a graphene pattern. The graphitization catalyst is one or more selected from Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Mo, Rh, Si, Ta, Ti, W, U, V, and Zr.
Abstract translation: 目的：提供一种使用压印技术形成石墨烯图案的方法，以便通过基于电子场来实现石墨烯转印处理，通过调节电压的强度来容易地调节转印石墨烯的厚度。 构成：准备在母板（200）上形成有图案（205）的压印印模（210）。 在压印印模上形成含有石墨化催化剂的金属膜（220）。 石墨烯（230）形成在印记上。 将石墨烯转移到用于制造器件的衬底（240）以形成石墨烯图案。 石墨化催化剂是选自Ni，Co，Fe，Pt，Au，Al，Cr，Cu，Mg，Mn，Mo，Rh，Si，Ta，Ti，W，U，V和Zr中的一种或多种。
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公开(公告)号：KR1020210044519A
公开(公告)日：2021-04-23
申请号：KR1020190127781
申请日：2019-10-15
Applicant: (재)한국나노기술원
Abstract: 본발명에서는 10000um2 이하의발광부면적을갖는마이크로 LED 장치가개시된다. 본발명의일 실시예에따른마이크로 LED 장치는상기마이크로 LED 장치는 P형반도체, 발광부및 N형반도체가적층되는적층구조를포함하고, 상기발광부의사이드월바깥면에쇼키컨택된금속층이형성된다.
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公开(公告)号：KR101866298B1
公开(公告)日：2018-07-05
申请号：KR1020160184218
申请日：2016-12-30
Applicant: (재)한국나노기술원
IPC: H01L31/068 , H01L31/18 , H01L31/0224 , H01L31/055 , H01L31/0392
CPC classification number: Y02E10/52 , Y02P70/521 , H01L31/0684 , H01L31/022425 , H01L31/022441 , H01L31/03926 , H01L31/055 , H01L31/1868 , H01L31/1892 , Y02E10/50
Abstract: 본발명은양면수광형태양전지의제조방법및 그에의한양면수광형태양전지에관한것으로서, 지지기판상부에제1태양전지셀을형성하는제1단계와, 상기제1태양전지셀상부에오믹접촉층을형성하는제2단계와, 상기오믹접촉층상부에제2태양전지셀을형성하는제3단계와, 상기지지기판을제거하는제4단계와, 상기지지기판을제거한후, 상기제1태양전지셀의전면에제1전극을형성하는제5단계와, 상기제1전극의형성후 메사에칭에의한상기오믹접촉층하부에제2전극을형성하는제6단계와, 상기제2태양전지셀의전면에제3전극을형성하는제7단계및 상기제3전극의형성후 메사에칭에의한상기오믹접촉층상부에제4전극을형성하는제8단계를포함하여이루어지는것을특징으로하는양면수광형태양전지의제조방법및 그에의한양면수광형태양전지를기술적요지로한다. 이에의해본 발명은기존의양면수광형태양전지의구조에서탈피하여, 전면과후면태양전지셀이상호대칭되게형성되도록하여전면과후면태양전지셀의효율차이가없어양면수광형태양전지의효율을개선시킨이점이있다.
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49.发明公开진공증착에 의한 나노구조체 패턴 형성방법, 이를 이용한 센서 소자의 제조방법 및 이에 의해 제조된 센서 소자 有权通过真空沉积形成纳米结构图案的方法，使用该方法制造传感器元件的方法以及由此制造的传感器元件
公开(公告)号：KR1020180012385A
公开(公告)日：2018-02-06
申请号：KR1020160095038
申请日：2016-07-26
Applicant: (재)한국나노기술원
IPC: C23C14/04 , C23C14/54 , C23C14/06 , C23C14/58 , H01L21/033 , H01L29/78 , G01N27/414
CPC classification number: C23C14/042 , C23C14/06 , C23C14/54 , C23C14/542 , C23C14/58 , G01N27/4141 , H01L21/0337 , H01L29/0665 , H01L29/78
Abstract: 본발명은진공증착공정을이용하여나노구조체패턴을형성하기위한것으로서, 기재상부의일부영역을노출시키는마스크패턴층을형성하는제1단계와, 상기기재의노출된영역및 상기마스크패턴층상부에나노구조체의성장을위해필요한나노구조체의최소임계반지름을만족하는진공증착조건을설정하는제2단계와, 진공증착공정에의해상기기재의노출된영역및 상기마스크패턴층상부에나노구조체를성장시키는제3단계및 상기마스크패턴층을제거하여, 상기기재의노출된영역에나노구조체를형성하여상기기재상부에나노구조체패턴을형성하는제4단계를포함하여이루어지는것을특징으로하는진공증착에의한나노구조체패턴형성방법, 이를이용한센서소자의제조방법및 이에의해제조된센서소자를기술적요지로한다. 이에의해본 발명은나노구조체의성장을위해필요한나노구조체의최소임계반지름을만족하는진공증착조건을설정하여진공증착공정을이용하여기재상부에나노구조체패턴을형성함으로써, 공정이간단하면서균일한나노구조체분포를가지는나노구조체패턴의형성이용이하며, 열처리공정이필요하지않아고온에취약한고분자기판과같은유연기판상에서의나노구조체패턴을형성할수 있고, 나노구조체의형태및 두께변형등을최소화함으로써고품질의소자를제공할수 있는이점이있다.
Abstract translation: 用于形成使用真空沉积工艺形成纳米结构图案的本发明中，形成掩模图案层的第一步骤，以暴露一部分衬底上，在曝光区域和掩模图案层，基体材料的上部 设定真空沉积条件满足用于纳米结构的生长所需要的纳米结构的最小临界半径，使得由真空沉积工艺以在暴露的区域和掩模图案层生长纳米结构，所述基体材料的上部的第二步骤 第三步和通过利用真空蒸镀法去除掩模图案层，纳米包括在所述基板的暴露区域上形成纳米结构的第四步骤，以形成于基板顶部上的纳米结构图案 结构图案形成方法，使用其的传感器元件制造方法以及通过该方法制造的传感器元件。 因此，通过处理完毕发明通过设置真空沉积条件满足对使用真空沉积过程中银纳米结构的生长所需要的纳米结构的最小临界半径，以形成在基板上，一个和该过程的纳米结构图案是简单的，均匀的纳米结构 可以形成在易受高温影响的柔性衬底（例如聚合物衬底）上的纳米结构图案，并且可以最小化纳米结构的形状和厚度变形， 等等。
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公开(公告)号：KR101796006B1
公开(公告)日：2017-11-10
申请号：KR1020160036148
申请日：2016-03-25
Applicant: (재)한국나노기술원
IPC: H01L31/18 , H01L31/0224 , H01L31/049 , H01L31/0236 , H01L31/0392
CPC classification number: Y02E10/50
Abstract: 본발명은플렉시블태양전지의제조방법및 그에의해제조된플렉시블태양전지에관한것으로서, 벌크기판상부에반도체층을형성하는제1단계와, 상기반도체층상부에후면전극을형성하는제2단계와, 상기후면전극상부에홀패턴이구비된플렉시블기판을형성시키는제3단계와, 상기벌크기판을제거하는제4단계와, 상기반도체층하부에전면전극을형성하는제5단계와, 상기홀패턴내부에전도성재료를충진시키는제6단계및 상기전도성재료가홀패턴에충진된플렉시블기판전면에금속백시트를형성하는제7단계를포함하여이루어지는것을특징으로하는전도성기판을갖는플렉시블태양전지의제조방법및 그에의해제조된플렉시블태양전지그리고이를이용한플렉시블태양전지모듈을기술적요지로한다. 이에의해본 발명은홀패턴이구비된플렉시블기판을사용하고, 상기홀패턴에전도성재료를충진하여사용함으로써, 플라스틱재료의유연성과전도성재료의전도성을융합시킨전도성을갖는플렉시블기판을적용하여, 기존플렉시블기판사용시문제되는전기적및 열적특성을향상시켜태양전지의성능을개선시키고, 이러한홀패턴이구비된플렉시블기판을사용한플렉시블태양전지는직렬로연결하여모듈형태로사용할시에후면전극연결문제를해결하고, 무게를획기적으로줄일수 있는초경량플렉시블태양전지또는초경량플렉시블태양전지모듈을제공할수 있는이점이있다.
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