中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

70 records (took 0.025 seconds)

    Halbleiterbauteil mit Halbleiterchip und Verfahren zu dessen Herstellung
    44.
    发明专利
    Halbleiterbauteil mit Halbleiterchip und Verfahren zu dessen Herstellung 未知

    公开(公告)号：DE102007036841B4

    公开(公告)日：2018-05-09

    申请号：DE102007036841

    申请日：2007-08-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MAHLER JOACHIM DR ,  KESSLER ANGELA ,  HAIMERL ALFRED DR ,  BAUER MICHAEL DIPL -ING (FH) ,  SCHOBER WOLFGANG DR

    IPC: H01L23/498 ,  H01L21/58 ,  H01L21/60

    Abstract: Halbleiterbauteil aufweisend:- einen Halbleiterchip (3) mit wenigstens einem ersten Kontakt (5) und einem zweiten Kontakt (7) auf seiner Oberseite (8), wobei der Halbleiterchip (3) eine Rückseite (9) aufweist, auf der ein dritter Kontakt (6) angeordnet ist,- Außenkontakte (14 bis 18, 30 bis 33),- ein Strukturelement (25), aufweisend Verbindungselemente (24), die gemeinsam auf einem isolierenden Basisteil (23) des Strukturelements (25) angeordnet sind und welche den ersten Kontakt (5) und den zweiten Kontakt (7) der Oberseite (8) des Halbleiterchips (3) mit den Außenkontakten (30 bis 33) verbinden, wobei das Strukturelement (25) einen thermischen Ausdehnungskoeffizienten von weniger als 10 ppm/K aufweist und wobei das Strukturelement (25) eine Stufe (34) aufweist, wobei die Stufenhöhe (h) an die Dicke (D) des Halbleiterchips (3) angepasst ist.

    Elektronikbauelement, Verfahren zur Herstellung und Halbleiterbaustein
    46.
    发明专利
    Elektronikbauelement, Verfahren zur Herstellung und Halbleiterbaustein 未知

    公开(公告)号：DE102008058835B4

    公开(公告)日：2016-11-03

    申请号：DE102008058835

    申请日：2008-11-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KESSLER ANGELA ,  SCHOBER WOLFGANG ,  PETERS ROMAN

    IPC: H01L23/50 ,  H01L21/60

    Abstract: Elektronikbauelement (50; 320; 400; 500), umfassend: einen Träger (22; 322; 410; 510), der eine erste Oberfläche (38; 338; 411; 511) definiert, wobei der Träger (22; 322; 410; 510) ein direkt kupfergebondeter Träger (22; 322; 410; 510) ist, der eine erste Metallschicht (132), eine über der ersten Metallschicht (132) angeordnete Keramikschicht (130; 330) und eine über der Keramikschicht (130; 330) angeordnete zweite Metallschicht (134; 334) umfasst; einen Chip (24; 124; 324; 412; 512), der an der ersten Oberfläche (38; 338; 411; 511) angebracht ist, wobei der Chip (24; 124; 324; 412; 512) an der zweiten Metallschicht (134; 334) angebracht ist; eine Matrix (26; 126; 450) von Zuleitungen (28; 40; 140; 440; 540), die mit der ersten Oberfläche (38; 338; 411; 511) verbunden sind; und eine Schicht aus Kapselungsmaterial (52; 152; 404; 504), das auf der ersten Oberfläche (38; 338; 411; 511) des Trägers (22; 322; 410; 510) angeordnet ist; wobei jede Zuleitung (28; 40; 140; 440; 540) durch die Schicht des Kapselungsmaterials (52; 152; 404; 504) verläuft.

    47.
    发明专利
    未知

    公开(公告)号：DE102008058835A1

    公开(公告)日：2009-06-25

    申请号：DE102008058835

    申请日：2008-11-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KESSLER ANGELA ,  SCHOBER WOLFGANG ,  PETERS ROMAN

    IPC: H01L23/50 ,  H01L21/60

    Abstract: Embodiments provide an electronic device including a carrier defining a first major surface, a chip attached to the first major surface, an array of leads connected to the first major surface, and a thickness of encapsulation material disposed on the first major surface of the carrier. Each lead extends through the thickness of the encapsulation material.

    Semiconductor component comprises a semiconductor chip with contacts on its upper side, external contacts, connecting elements arranged together on a single-piece structural element, and a chip carrier having an upper side and a backside
    48.
    发明专利
    Semiconductor component comprises a semiconductor chip with contacts on its upper side, external contacts, connecting elements arranged together on a single-piece structural element, and a chip carrier having an upper side and a backside 未知

    公开(公告)号：DE102007036841A1

    公开(公告)日：2009-02-12

    申请号：DE102007036841

    申请日：2007-08-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MAHLER JOACHIM ,  KESSLER ANGELA ,  HAIMERL ALFRED ,  BAUER MICHAEL ,  SCHOBER WOLFGANG

    IPC: H01L23/498 ,  H01L21/58 ,  H01L21/60 ,  H01L23/043 ,  H01L23/31

    Abstract: The semiconductor component (1) comprises a semiconductor chip (3) with first and second contacts on its upper side (8), external contacts (14, 15, 16, 17, 18), connecting elements (24) arranged together on a single-piece structural element (25), which has direct copper bonded (DCB)-material, and a chip carrier having an upper side and a backside. The connecting elements connect the first and second contacts with the external contacts. Each of the connecting elements has two contact surfaces and a conducting path. The semiconductor chip has a backside, on which a third contact is arranged. The semiconductor component (1) comprises a semiconductor chip (3) with first and second contacts on its upper side (8), external contacts (14, 15, 16, 17, 18), connecting elements (24) arranged together on a single-piece structural element (25), which has direct copper bonded (DCB)-material, and a chip carrier having an upper side and a backside. The connecting elements connect the first and second contacts with the external contacts. Each of the connecting elements has two contact surfaces and a conducting path. The semiconductor chip has a backside, on which a third contact is arranged. The DCB-material has an one-side copper-coated ceramic plate based on aluminum oxide and aluminum nitride, and a structured copper layer with a thickness (d) of 100-600 mu m. The thermal expansion coefficient of the DCB-material is adjusted to 7.1 ppm/K for aluminum oxide and 4.1 ppm/k for aluminum nitride during suitable mixing of the ceramics at the thermal expansion coefficient of silicon. The structure of the copper layer is adjusted to the electrodes on the upper side of the power semiconductor chip, and has a signal conducting path for connecting a gate electrode and a power conducting path for connecting a power electrode. The structural component stretches itself between the upper side of the semiconductor chip and the two separate external contacts. The first contact is electrically connected over the conducting path with the external contacts. The structural element has a thermal expansion coefficient of 10 ppm/K. The structural element has a preformed base part, which is made of plastic/sintered ceramics and has insulating fillers. The thermal expansion coefficient of the preformed base part is adjusted to the thermal expansion coefficient of the semiconductor material of the semiconductor ship. The structural element has conducting paths and contact surfaces. The cross section of the conducting paths is adjusted to the current density, which flows over the contacts. The structural element has a coating structured to the conducting paths and the contact surfaces. Flat conductors form the external contacts, which form the surface-mountable flat external contacts of the semiconductor component. The first and the second contacts of the upper side of the chip form a common contact-connection level with associated contact surfaces of the structural element and are surface-mountable. The contacts of the upper side and the contact surfaces of the structural element have coatings diffusion slot components for forming inter-metallic phases. The structural element has a pitch, an obtuse support and a planar connecting plate. The height of the pitch and the obtuse support is adjusted to the thickness of the semiconductor chip. The external contacts are preformed for equalizing the thickness and carry the semiconductor chip. The third contact covers the backside as single backside electrode. The semiconductor component has a diffusion slot layer between the third contact and the assigned chip carrier. The first contact is a second power electrode and the second contact is the gate electrode. The second power electrode is a source electrode, the first power output electrode is a drain electrode of a vertical power metal oxide semiconductor field effect transistor (MOSFETs), and the gate electrode is an insulating gate electrode. The structural element has further contact surfaces for signal- and/or supply electrodes of the upper side of the semiconductor chip, which is provided with a monolithic integrated gate circuit and/or logic circuit. The power MOSFET has a monolithic integrated gate driver. The first contact is an emitter electrode, the third contact is a collector electrode of a vertical insulated gate bipolar transistor (IGBT), and the second contact is the insulating gate electrode. The gate electrode of the chip has a vertical trench gate electrode. The semiconductor component has a cavity housing, in which the chip, the structural element and upper side of the external contacts are arranged. The lower side of the external contacts is freely accessible on the lower side and/or the edge sides of the semiconductor component. The semiconductor component has a plastic housing, in which plastic housing mass of the chip, the structural element and surfaces of the external contacts are embedded. The lower sides of the external contacts of the flat conductor on the lower side of the semiconductor component and/or the upper side of the structural element on the upper side of the semiconductor element are freely held by plastic housing mass. The chip is arranged on the carrier. The backside of the chip carrier is freely accessible by the plastic housing mass. The backside of the chip carrier provides for an external contact of the semiconductor component. An independent claim is included for a method for the production of a component.

    49.
    发明专利
    未知

    公开(公告)号：DE102007002807A1

    公开(公告)日：2008-10-02

    申请号：DE102007002807

    申请日：2007-01-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MAHLER JOACHIM ,  HAIMERL ALFRED ,  KESSLER ANGELA ,  BAUER MICHAEL

    IPC: H01L25/04

    Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.

    50.
    发明专利
    未知

    公开(公告)号：DE102005049687A1

    公开(公告)日：2007-04-26

    申请号：DE102005049687

    申请日：2005-10-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BAUER MICHAEL ,  KESSLER ANGELA ,  SCHOBER WOLFGANG ,  HAIMERL ALFRED ,  MAHLER JOACHIM

    IPC: H01L23/48

    Abstract: One aspect of the invention relates to a power semiconductor device in lead frame technology and a method for producing the same. The power semiconductor device has a vertical current path through a power semiconductor chip. The power semiconductor chip has at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a lead frame chip island of a lead frame and the top side electrode is electrically connected to an internal lead of the lead frame via a connecting element. The connecting element has an electrically conductive film on a surface facing the top side electrode, the electrically conductive film extending from the top side electrode to the internal lead.

Patent Agency Ranking