公开(公告)号：DE10125370C1

公开(公告)日：2002-11-14

申请号：DE10125370

申请日：2001-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  MOERT MANFRED ,  SCHINDLER GUENTHER ,  WEINRICH VOLKER

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8239

Abstract: The manufacturing method has a dielectric or ferroelectric layer for integrated capacitors (2) of the semiconductor circuit deposited on an intermediate carrier, which is heated for conversion of the dielectric or ferroelectric layer into a highly polarized phase. The dielectric or ferroelectric layer is subsequently released from the intermediate carrier and reduced into small particles (4) applied to the semiconductor substrate (1) for the semiconductor circuit.

公开(公告)号：DE19963500C2

公开(公告)日：2002-10-02

申请号：DE19963500

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER ,  WEINRICH VOLKER ,  AHLSTEDT MATTIAS

IPC: H01L21/316 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L21/321 ,  C23C14/08 ,  C23C16/40

Abstract: The damage to edge sections which occurs during the patterning of a metal-oxide-containing layer can be compensated by the deposition of an annealing layer and a subsequent heat treatment step through which a material flow takes place from the annealing layer into the damaged edge sections. The metal-oxide-containing layer can form the dielectric of a storage capacitor of a DRAM memory cell.

公开(公告)号：DE10041685C2

公开(公告)日：2002-06-27

申请号：DE10041685

申请日：2000-08-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER ,  GABRIC ZVONIMIR

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L21/8239

Abstract: Production of a microelectronic component comprises: (i) forming a storage capacitor containing a first electrode, a second electrode and a ferroelectric or paraelectric dielectric on a substrate; and (ii) forming a barrier on the capacitor to prevent the hydrogen passing through. The hydrogen barrier is produced by forming a silicon oxide layer (41), tempering the capacitor and at least a part of the silicon oxide layer, and applying a barrier layer (42) to the tempered silicon oxide layer. Preferred Features: At least a part of the barrier layer is applied in a hydrogen-free deposition process. A first partial layer of the barrier layer is initially applied followed by a second partial layer of silicon nitride. The silicon nitride layer is deposited using a low pressure microwave process. The silicon oxide layer has partial layers (411, 412).

公开(公告)号：DE10022655C2

公开(公告)日：2002-03-07

申请号：DE10022655

申请日：2000-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  HARTNER WALTER ,  SCHNABEL RAINER-FLORIAN

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01G4/33 ,  H01G4/40

Abstract: The invention relates to a method for producing at least one capacitor structure, comprising the following steps: providing a substrate, producing a first electrode on said substrate, producing a mask, whereby the first electrode is disposed in an opening of said mask, and applying at least one dielectric layer and at least one conductive layer for a second eletrode. The surface of the part of the conductive layer that is applied in the opening of the mask is substantially disposed below the surface of the mask. The conductive layer and the dielectric layer are structured by polishing so that a capacitor structure is produced.

公开(公告)号：DE10001118A1

公开(公告)日：2001-07-26

申请号：DE10001118

申请日：2000-01-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER ,  KASTNER MARCUS

IPC: H01L21/8242 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/108

Abstract: Production of a semiconductor component involves forming switching transistor (2) on semiconductor substrate, applying a first insulating layer (4) to the transistor, applying a storage capacitor (3) containing a lower (31) and an upper electrode (33a) and a metal oxide -containing layer to the insulating layer, and applying a second insulating layer (5) to the capacitor. The electrodes contain a platinum metal or a conducting oxide of a platinum metal. A conducting protective layer (33b) is applied to the upper electrode in a contact opening (51) which is filled with tungsten by chemical vapor deposition in a hydrogen atmosphere. Preferred Features: The electrodes contain platinum or consist of platinum. The metal oxide-containing layer is made of SrBi2(Ta, Nb)2O9, Pb(ZrTi)O3 or Bi4Ti3O12. The protective layer is made of WSi, IrOx, RhOx, RuOx, OsOx, SrRuO3, LaSrCoOx, a high temperature superconductor or carbide.

公开(公告)号：DE102013015724A1

公开(公告)日：2014-03-20

申请号：DE102013015724

申请日：2013-09-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRASE GABRIELA ,  NELLE PETER ,  SCHINDLER GUENTHER ,  ZUNDEL MARKUS

IPC: H01L29/06 ,  H01L21/76 ,  H01L29/739 ,  H01L29/78

Abstract: Die Beschreibung bezieht sich auf Halbleiterbauelement mit einem Halbleiterkörper, einer Isolation an dem Halbleiterkörper und einem Zellenfeld, welches zumindest teilweise in dem Halbeleiterkörper angeordnet ist. Das Zellenfeld weist zumindest einen p–n Übergang und zumindest eine Kontaktierung auf. Die Isolation ist in lateraler Richtung des Halbleiterkörpers von einer umlaufenden Diffusionsbarriere begrenzt.

公开(公告)号：DE102005039323A1

公开(公告)日：2007-02-22

申请号：DE102005039323

申请日：2005-08-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GABRIC ZVONIMIR ,  STICH ANDREAS ,  PAMLER WERNER ,  SCHINDLER GUENTHER

IPC: H01L23/522 ,  H01L21/768

Abstract: A conduction path arrangement has a substrate (1,2), at least two conduction paths (4), formed adjacent to one another over the substrate, and a cavity which is formed at least between the conduction paths (4), and a dielectric covering layer (5) covering the conduction paths and enclosing the cavity. The support paths (TB) between the substrate (1,2) and the conduction paths (4) are designed to support the conduction paths, in which on the contact surface, a width (B1) of the conduction paths is greater than a width (B2) of the support paths (TB). An independent claim is included for a method for fabrication a conduction path arrangement.

公开(公告)号：DE102005008476A1

公开(公告)日：2006-09-14

申请号：DE102005008476

申请日：2005-02-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  PAMLER WERNER ,  ENGELHARDT MANFRED

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/108

Abstract: An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.

公开(公告)号：DE102005001893B3

公开(公告)日：2006-06-08

申请号：DE102005001893

申请日：2005-01-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  SCHINDLER GUENTHER

IPC: H01L27/105 ,  H01L21/8239

Abstract: A ferroelctric RAM memory comprises ferroelectric memory capacitors above a lateral series of select transistors (3) in a substrate (1,2) whose electrodes (14a,b) are connected pairwise laterally and joined to the transistors by vertical plugs (20). Air gaps between transistors in two lateral dimensions mechanically decouple the capacitors. An independent claim is also included for a production process for the above.

公开(公告)号：DE10341544B4

公开(公告)日：2005-10-13

申请号：DE10341544

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  PAMLER WERNER ,  GABRIC ZVONIMIR ,  UNGER EUGEN

IPC: H01L21/768 ,  H01L23/522