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    MANUFACTURE OF HIGH DENSE MOS TYPE ELECTRIC POWER DEVICE ANDHIGH DENSE TYPE ELECTRIC POWER DEVICE MANUFACTURED BY ITS METHOD
    57.
    发明专利
    MANUFACTURE OF HIGH DENSE MOS TYPE ELECTRIC POWER DEVICE ANDHIGH DENSE TYPE ELECTRIC POWER DEVICE MANUFACTURED BY ITS METHOD 失效

    公开(公告)号：JPH0897168A

    公开(公告)日：1996-04-12

    申请号：JP16869395

    申请日：1995-07-04

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of highly integrated MOS power device. SOLUTION: Insulating gate layers 8 and insulating layers 11 are formed on a semiconductor layer 2, next to a plurality of slender windows having long edges 17 and short edges sectioning respectively exposed surface fine strips 16 are formed by selectively removing layers 8 and 11. Then the slender windows are implanted with a first dopant vertically thereto and perpendicularly to the layer 2 so as to be symmetrically tilted at the surface of the layer 2 making an angle. These angles depending upon the gross thickness of the layers 8 and 11 for preventing the first dopant from being implanted into the central fine strips of the fine strips 16 to form the pairs of source regions 6 extending along the edges 17 of respective windows, also separated by the central fine strips further symmetrically tilted making another angle to be implanted with a second dopant to form respective regions with two channel regions 5, extending to the under side of the long edges of respective windows finally implanted with a third dopant to form the regions aligned with the edges 17 of the windows using the layers 11 as masks.

    ELECTRIC SWITCH FOR LOW VOLTAGE INTEGRATED POWER CIRCUIT
    58.
    发明专利
    ELECTRIC SWITCH FOR LOW VOLTAGE INTEGRATED POWER CIRCUIT 失效

    公开(公告)号：JPH0865124A

    公开(公告)日：1996-03-08

    申请号：JP19462395

    申请日：1995-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  NICOLLINI GERMANO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H03K17/687

    Abstract: PROBLEM TO BE SOLVED: To provide an electronic switch with which no body effect occur by suitably connecting the substrate of complementary transistor to the maximum and minimum potential references of integrated circuit(IC). SOLUTION: Between connecting terminals A and B, the source and drain of 1st and 2nd P channel transistors M1 and M2 are serially inserted. A transistor M3 composed of (n) channels is connected to the node of M1 and M2 and between them, a minimum electric reference Vss of IC having the electronic switch is inserted. Besides, a transistor M4 composed of (n) channels is inserted between the terminals A and B of M1 and M2 through source and drain terminals, and the substrates of M1 and M2 are connected to the terminals A and B. The substrates of M3 and M4 are connected to the reference Vss as well and M4 is driven by the inverse of ϕ signal through a gate terminal but M1 and M2 are driven by an opposite signal ϕ. The inverse of ϕsignal is impressed to M3, which can be driven by the signal ϕthrough the terminals of M1 and M2 and inverters, and this reference is defined as a maximum voltage reference.

    INITIALIZING CIRCUIT
    59.
    发明专利
    INITIALIZING CIRCUIT 失效

    公开(公告)号：JPH0856144A

    公开(公告)日：1996-02-27

    申请号：JP13085995

    申请日：1995-05-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  NICOLLINI GERMANO

    IPC: G06F1/24 ,  G11C7/22 ,  H03K3/356 ,  H03K17/00 ,  H03K17/22

    Abstract: PURPOSE: To avoid the waste of power by setting the voltage of a circuit node B to be a zero value at the same time of setting the voltage of a circuit node A to be a supply power source voltage so as to make power consumption close to zero in a normal state. CONSTITUTION: When a supply power source voltage Vp is boosted, the voltage Va of the circuit node A is boosted to a value equal to the threshold value voltage Vt of a transistor(Tr)MN1 by time t2 . As resistance R1 is extremely high, at the additional and small boost of voltage δN, the node A is stabilized by the voltage value of Vn =Vt +δN. TrMP1 is maintained to be off until voltage between the voltage Vp and a gate terminal G3 reaches the conductive threshold value V of P-channel Tr. Though the boost of voltage δP at this point of time is small, negative impedance is added to the P-channel of TrMP1 to boost the voltage of the node B to the same value as Vp . Consequently, until the voltage Vp reaches a tripping threshold value VS, a voltage at the node B is zero In addition, as the result that a zero voltage value exists at the circuit node of a circuit part 4 at t1 , the voltage Vp exists on the gate terminal G2 of TrMN 2, voltage drop between a drain terminal D2 and the ground GND can be neglected.

    FACTORY TEST METHOD OF FLASH EEPROM DEVICE
    60.
    发明专利
    FACTORY TEST METHOD OF FLASH EEPROM DEVICE 失效

    公开(公告)号：JPH0855499A

    公开(公告)日：1996-02-27

    申请号：JP13943595

    申请日：1995-06-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAZZALI STEFANO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/10 ,  G11C29/24 ,  G11C29/52 ,  G11C29/56

    Abstract: PURPOSE: To obtain the factory testing method for a flash EEPROM element which suitably discriminates the presence of a fast erasure bit. CONSTITUTION: This element is equipped with a matrix of memory cells 1 and a redundant memory cell 1' which substitutes functionally for a defective memory cell 1". Then all the memory cells 1 of the memory element are programmed and all the memory cells 1 of the memory element are erased preliminarily and electrically in a time much shorter than the mean erasure time of the memory cells 1. Information stored in all the memory cell 1 of the memory element is read out. The address of the defective memory cell 1" which is read as an erased memory cell is remembered. The address of the defective memory cell 1" is stored in redundancy registers 15 and 20 of the memory element which relate to the redundant memory cell 1' that should substitute for the defective memory cell 1".

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