公开(公告)号：DE102005013300A1

公开(公告)日：2006-09-28

申请号：DE102005013300

申请日：2005-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  MECKES ANDREAS ,  OPPERMANN KLAUS-GUENTER

IPC: B81C1/00 ,  B29C59/02 ,  H03H3/00

Abstract: To form a polymer structure (21) on a defined zone of a substrate (11) surface, an adhesive bonding layer (13) is applied using one polymer material. The bond is removed from the surface leaving a bonding layer island (15) in the required location. A further layer (17) is applied, of a second polymer, and cleaned off leaving a layer cover (19) over the first island layer for a polymer structure of the required height (23) and width (25). The layers are of a SU-8 photo varnish of different viscosities containing different plastics components.

公开(公告)号：DE102005004795A1

公开(公告)日：2006-08-17

申请号：DE102005004795

申请日：2005-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  MECKES ANDREAS ,  OPPERMANN KLAUS-GUENTER

IPC: B81C1/00 ,  H01L21/306

Abstract: The method involves bringing a reactive material (16) in contact with a wet-chemical treatment unit (24) through an access opening in a material structure (12) for removing the material from the structure. A mechanical oscillation is produced in the unit or in the structure, when the material is brought into contact with the unit. The unit has a treatment area surrounded by a cover structure and a substrate of the structure (12). An independent claim is also included for a device for wet-chemical removal of a reactive material in a material structure, comprising a generating unit.

公开(公告)号：DE10353767B4

公开(公告)日：2005-09-29

申请号：DE10353767

申请日：2003-11-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  MECKES ANDREAS ,  OPPERMANN KLAUS-GUENTER

IPC: B81B7/00 ,  B81C1/00

公开(公告)号：DE50300607D1

公开(公告)日：2005-07-07

申请号：DE50300607

申请日：2003-01-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AIGNER ROBERT ,  FRANOSCH MARTIN ,  MECKES ANDREAS ,  OPPERMANN KLAUS-GUENTER ,  STRASSER MARC

IPC: B81B7/00 ,  H03H9/10

公开(公告)号：DE10200869A1

公开(公告)日：2003-07-31

申请号：DE10200869

申请日：2002-01-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OPPERMANN KLAUS-GUENTER ,  FRANOSCH MARTIN ,  AIGNER ROBERT ,  MECKES ANDREAS

IPC: B81B7/00 ,  B81C1/00 ,  H03H3/02 ,  H01L21/56 ,  B81B3/00 ,  H03H9/64 ,  H03H3/08

Abstract: In a method for generating a protective cover for a device, where a substrate is provided, which comprises the device, first, a sacrificial pattern is generated on the substrate. The sacrificial pattern covers at least an area of the substrate, which comprises the device. Then, a polymer layer is deposited, which comprises at least on sacrificial pattern. Then, an opening will be formed in the polymer layer to expose a portion of the sacrificial pattern. Then, the sacrificial pattern will be removed and the formed opening in the polymer layer is closed.

公开(公告)号：DE10063991A1

公开(公告)日：2002-07-04

申请号：DE10063991

申请日：2000-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PUSCH CATHARINA ,  WITTMANN REINHARD ,  FRANOSCH MARTIN

IPC: B81B3/00 ,  B81C1/00

Abstract: A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be undercut includes forming at least one etch hole in the layer, which is to be undercut, and providing at least one passivation layer for controlling a selective depositing of a cover material which closes each of the etch holes after a step of etching the sacrificial layer. The passivation layer makes it possible that the undercut layer elements do not become excessively thick or grow together with the substrate due to the deposition of the cover material.

公开(公告)号：DE19821901C2

公开(公告)日：2002-05-08

申请号：DE19821901

申请日：1998-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  GRUENING ULRIKE ,  LEHMANN VOLKER ,  WENDT HERMANN ,  WILLER JOSEF ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

IPC: H01L21/8244 ,  H01L27/11 ,  G11C11/412

Abstract: An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

公开(公告)号：DE19958062A1

公开(公告)日：2001-07-05

申请号：DE19958062

申请日：1999-12-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  MEISTER THOMAS F ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN ,  BOECK JOSEF ,  KLEIN WOLFGANG

IPC: H01L21/331 ,  H01L29/732 ,  H01L27/082

Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

公开(公告)号：DE19933564C1

公开(公告)日：2001-01-25

申请号：DE19933564

申请日：1999-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L29/78

Abstract: According to the invention, a double gate MOSFET semiconductor layer structure is formed on a substrate (1). This structure is comprised of a first and of a second gate electrode (10A, 10B) between which a semiconductor channel layer zone (4A) is embedded, and of a source region (2A) and a drain region (2B) which are arranged on opposite faces of the semiconductor channel layer zone (4A). At least one additional semiconductor channel layer zone (6A) is provided on one of the gate electrodes (10B). The faces of the at least one additional semiconductor channel layer zone are also contacted by the source region (2A) and drain region (2B).