公开(公告)号：DE10009762A1

公开(公告)日：2001-09-20

申请号：DE10009762

申请日：2000-03-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  BACHHOFER HARALD ,  HOENLEIN WOLFGANG ,  SCHINDLER GUENTHER ,  HARTNER WALTER

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: Production of a storage capacitor comprises preparing a first electrode layer (1); applying a 1 nm thick CeO2 layer (2) on the electrode layer; applying an amorphous dielectric layer (3) made from SrBi2Ta2O9 (SBT) or SrBi2(TaNb)2O9 (SBTN) on the CeO2 layer; heating at 590-620[deg] C to crystallize the dielectric layer; and applying a second electrode layer (4) on the dielectric layer. An independent claim is also included for a process for the production of a semiconductor component comprising forming a switching transistor on a semiconductor substrate; and forming the storage capacitor on the transistor. Preferred Features: The electrode layers are made from platinum, a conducting oxide of a platinum or an inert and conducting oxide. The dielectric layer is 20-200 nm thick.

公开(公告)号：DE19963500A1

公开(公告)日：2001-07-26

申请号：DE19963500

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER ,  WEINRICH VOLKER ,  AHLSTEDT MATTIAS

IPC: H01L21/316 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L21/321 ,  C23C16/40

Abstract: The damage to edge sections which occurs during the patterning of a metal-oxide-containing layer can be compensated by the deposition of an annealing layer and a subsequent heat treatment step through which a material flow takes place from the annealing layer into the damaged edge sections. The metal-oxide-containing layer can form the dielectric of a storage capacitor of a DRAM memory cell.

公开(公告)号：DE19957122A1

公开(公告)日：2001-06-28

申请号：DE19957122

申请日：1999-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  HARTNER WALTER

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/314 ,  H01L27/115 ,  H01L27/11502 ,  H01G7/06 ,  H01L21/8239

Abstract: Production of a ferroelectric capacitor (10) on a semiconductor substrate (1) comprises producing first electrode (11); depositing ferroelectric capacitor material (13) over first electrode; producing second electrode (12) over the ferroelectric capacitor material; and applying an alternating voltage on the capacitor so that current loss in the capacitor is reduced by more than a factor of 10. An Independent claim is also included for the capacitor produced. Preferred Features: The second electrode is made from Al, W, Cu, TiNx, WNx, TaNx, TiWNx, WSix, TiSix or TaSix.

公开(公告)号：DE19935131A1

公开(公告)日：2001-02-08

申请号：DE19935131

申请日：1999-07-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERGMANN RENATE ,  DEHM CHRISTINE ,  HASLER BARBARA ,  SCHELER ULRICH ,  SCHINDLER GUENTHER ,  WEINRICH VOLKER ,  HARTNER WALTER

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/8239 ,  H01L27/08

Abstract: The invention relates to a method for removing redepositions on a wafer and to a wafer which is devoid of redepositions. The removal of the redepositions on the wafer occurs after a protective layer is arranged on the top electrode and the boundary surfaces of the electrodes with a dielectric, whereby said areas are not damaged by wet chemical agents enabling the redepositions to be exclusively and efficiently removed.

公开(公告)号：DE50213004D1

公开(公告)日：2008-12-24

申请号：DE50213004

申请日：2002-03-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGELHARDT MANFRED ,  SCHINDLER GUENTHER

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: An interconnect arrangement ( 100 ) has a first layer ( 101 ), a first layer surface ( 102 ), thereon at least two interconnects ( 104 ) having a second layer surface ( 105 ) essentially parallel to the first layer surface ( 102 ), thereon a respective second layer ( 106 ) for each interconnect ( 104 ), the second layers ( 106 ) of adjacent interconnects covering regions between the adjacent interconnects ( 104 ), and thereon a third layer ( 107 ), which completely closes off the regions between the adjacent interconnects ( 104 ) by means of coverage.

公开(公告)号：DE10058965B4

公开(公告)日：2007-10-11

申请号：DE10058965

申请日：2000-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  KROENKE MATTHIAS

IPC: G11C7/00 ,  G11C7/20 ,  G11C11/22 ,  G11C11/401 ,  G11C11/404

公开(公告)号：DE102004037336B4

公开(公告)日：2006-09-21

申请号：DE102004037336

申请日：2004-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  PAMLER WERNER

IPC: H01L21/768 ,  H01L23/522 ,  H05K3/00

Abstract: A process for producing a layer arrangement, in which a plurality of electrically conductive structures are formed on a substrate, a first electrically insulating layer is formed on the plurality of electrically conductive structures, in such a manner than trenches are formed between mutually adjacent regions of the first electrically insulating layer, electrically insulating structures are formed in the trenches between the adjacent regions of the first electrically insulating layer, material of the first electrically insulating layer is removed, so that airgaps are formed between the electrically insulating structures and the electrically conductive structures, and a second electrically insulating layer is formed on the electrically conductive structures and on the electrically insulating structures, in such a manner that the second electrically insulating layer spans adjacent electrically conductive structures and electrically insulating structures.

公开(公告)号：DE102005004365A1

公开(公告)日：2006-08-10

申请号：DE102005004365

申请日：2005-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STEINLESBERGER GERNOT ,  STEINHOEGL WERNER ,  DUESBERG GEORG ,  SCHINDLER GUENTHER

IPC: H01L21/768 ,  H01L23/522

Abstract: The method involves creating a through-hole (403) through a substrate of an integrated circuit arrangement, where the hole passes from a cover surface to a base surface of the arrangement. An electrically conductive nucleation layer (402) is superimposed at the base surface or cover surface before or after creating the hole. An electrically conductive material of a conducting structure is galvanically deposited in the hole. An independent claim is also included for an integrated circuit arrangement comprising a conducting structure.

公开(公告)号：DE19935131B4

公开(公告)日：2006-01-26

申请号：DE19935131

申请日：1999-07-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERGMANN RENATE ,  DEHM CHRISTINE ,  HASLER BARBARA ,  SCHELER ULRICH ,  SCHINDLER GUENTHER ,  WEINRICH VOLKER ,  HARTNER WALTER

IPC: H01L21/02 ,  H01L21/302 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8239 ,  H01L27/08

公开(公告)号：DE19639899B4

公开(公告)日：2005-07-07

申请号：DE19639899

申请日：1996-09-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESPEJO-MAZURE CARLOS ,  SCHINDLER GUENTHER ,  HARTNER WALTER

IPC: H01L21/8242 ,  H01L27/108

Abstract: The invention concerns a storage arrangement (1) which consists of identical storage cells and comprises storage capacitors which are disposed above the selection transistors and whose first electrodes (14) are strip-shaped and disposed perpendicularly on a first main surface (2). The surfaces of the first electrodes (14) and hence the capacitor surfaces can be varied, for example, by varying the heights of the first electrodes (14) or, when the cell surfaces (5) are sensibly arranged, by overlapping cell surfaces (5) adjacent the first electrodes (14).