-
公开(公告)号：KR1020140130911A
公开(公告)日：2014-11-12
申请号：KR1020130049478
申请日：2013-05-02
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/66795 , H01L29/495 , H01L29/66545 , H01L29/66818 , H01L29/785
Abstract: 핀형 트랜지스터의 채널 영역에 균일한 스트레스를 인가할 수 있는 반도체 소자 제조 방법을 제공하는 것이다. 상기 반도체 소자 제조 방법은 기판 상에 돌출된 핀형 액티브 패턴을 형성하고, 상기 핀형 액티브 패턴 상에 상기 핀형 액티브 패턴과 교차하는 게이트 패턴을 형성하고, 상기 게이트 패턴의 측벽에 게이트 스페이서를 형성하고, 상기 게이트 스페이서의 측면과 정렬되는 측벽을 포함하는 제1 리세스를 상기 핀형 액티브 패턴 내에 형성하고, 게르마늄을 포함하는 가스를 이용하여 제1 리세스를 열처리하여, 제2 리세스를 형성하는 것을 포함한다.
Abstract translation: 本发明涉及一种用于制造半导体器件的方法，该半导体器件能够对鳍式晶体管的沟道区域施加均匀的应力。 制造半导体器件的方法包括：形成从衬底突出的鳍型有源图案，在翅片型有源图案上形成与鳍型有源图案相交的栅极图案，在栅极图案的侧壁中形成栅极间隔，形成 所述翅片型有源图案包括设置有所述栅极间隔物的侧表面的所述侧壁的第一凹部，以及通过使用包括Ge的气体在所述第一凹部上进行热处理而形成第二凹部。
-
公开(公告)号：KR101378469B1
公开(公告)日：2014-03-28
申请号：KR1020080042251
申请日：2008-05-07
Applicant: 삼성전자주식회사
CPC classification number: H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76846 , H01L21/76855 , H01L23/485 , H01L27/24 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
Abstract: 개선된 열적 안정성 및 전기적 특성을 갖는 콘택 구조물의 형성 방법에 있어서, 콘택 영역을 갖는 대상체 상에 절연층을 형성한 후, 절연층을 식각하여 콘택 영역을 노출시키는 개구를 형성한다. 노출된 콘택 영역 상에 실리콘 및 산소를 포함하는 물질막을 형성한 다음, 실리콘 및 산소를 포함하는 물질막 상에 금속막을 형성한다. 실리콘 및 산소를 포함하는 물질막과 금속막을 반응시켜 적어도 콘택 영역 상에 금속 산화물 실리사이드막을 형성한 후, 금속 산화물 실리사이드막 상에 개구를 채우는 도전막을 형성한다. 콘택 영역과 콘택 사이에 금속, 실리콘 및 산소가 삼성 분계를 이루는 금속 산화물 실리사이드막을 균일하게 형성할 수 있으므로, 금속 산화물 실리사이드막의 응집 현상을 효과적으로 방지하여 우수한 열적 및 전기적 안정성을 확보할 수 있고, 콘택의 계면 저항을 감소시킬 수 있다.
-
公开(公告)号：KR1020120038280A
公开(公告)日：2012-04-23
申请号：KR1020100099956
申请日：2010-10-13
Applicant: 삼성전자주식회사
IPC: H01L21/8238 , H01L21/02 , H01L21/311 , H01L29/165 , H01L29/417 , H01L29/66 , H01L29/78
CPC classification number: H01L21/823814 , H01L21/02068 , H01L21/31116 , H01L21/823807 , H01L21/823864 , H01L29/165 , H01L29/41775 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to remove a part of a spacer and a mask oxide layer without damaging a silicide layer. CONSTITUTION: A dummy gate pattern is formed on a substrate(100) including an NMOS area(10) and a PMOS area(20). A spacer structure is formed on a sidewall of the gate pattern. A recess region is formed on the exposed substrate of the PMOS area exposed by the spacer structure and the gate pattern. A compression stress pattern(170) is formed in the recess area. A mask oxide layer is formed on the sidewall of the spacer structure.
Abstract translation: 目的：提供半导体器件及其制造方法来去除间隔物的一部分和掩模氧化物层，而不会损坏硅化物层。 构成：在包括NMOS区域（10）和PMOS区域（20）的衬底（100）上形成伪栅极图案。 间隔结构形成在栅极图案的侧壁上。 在由间隔结构和栅极图案露出的PMOS区域的暴露的衬底上形成凹陷区域。 在凹部区域形成有压缩应力图案（170）。 在间隔结构的侧壁上形成掩模氧化物层。
-
公开(公告)号：KR1020110128468A
公开(公告)日：2011-11-30
申请号：KR1020100047930
申请日：2010-05-24
Applicant: 삼성전자주식회사
IPC: H01L21/027 , H01L21/336 , H01L29/78
CPC classification number: H01L21/28123 , H01L21/28273 , H01L21/3081 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L27/11524 , H01L21/0274 , H01L29/7803
Abstract: PURPOSE: A pattern formation method and a gate structure formation method are provided to form an excellent pattern by preventing the damage of an etching object film when eliminating a mask and to reduce the aspect ratio of a gate structure. CONSTITUTION: An etching object film which includes oxide in which impurity is not doped is formed on a substrate(300). A conductive film is formed on the etching object film. A mask which includes oxide in which the impurity is doped is formed on the etching object film. The etching object film is patterned using the mask. The conductive film is patterned. The mask is eliminated using gas which includes hydrogen fluoride. The gas comprises deionizer water vapor. The mask comprises BPSG(Boron Phosphorous Silica Glass). The etching object film comprises silicon oxide.
Abstract translation: 目的：提供图案形成方法和栅极结构形成方法以通过在消除掩模时防止蚀刻对象膜的损坏并且减小栅极结构的纵横比来形成优异的图案。 构成：在衬底（300）上形成包括不掺杂杂质的氧化物的蚀刻对象膜。 在蚀刻对象膜上形成导电膜。 在蚀刻对象膜上形成有包含掺杂杂质的氧化物的掩模。 使用掩模对蚀刻对象膜进行图案化。 导电膜被图案化。 使用包括氟化氢的气体来消除掩模。 气体包括去离子水蒸汽。 掩模包括BPSG（硼磷硅玻璃）。 蚀刻对象膜包括氧化硅。
-
公开(公告)号：KR1020100019328A
公开(公告)日：2010-02-18
申请号：KR1020090063235
申请日：2009-07-10
IPC: C09K13/08
Abstract: PURPOSE: A composition for etching a silicon oxide layer is provided to lowering an etching rate of various nitride layers while maintaining high etching rate of various silicon oxide layers presented a substrate. CONSTITUTION: A composition for etching a silicon oxide layer comprises hydrogen fluoride, anionic polymer and deionized water. The anionic polymer is included in the amount of 0.001-2 weight% based on the total amount of the composition for etching a silicon oxide layer. The etching selectivity of a silicon oxide layer to a nitride layer is 80 or more. The anionic polymer is selected from the group consisting of polyacrylic acid, polysulfonic acid, polyacrylamide/acrylic acid copolymer, polyacrylic acid/sulfonic acid copolymer, polysulfonic acid/acrylamide copolymer, polyacrylic acid/malonic acid copolymer, and their combination.
Abstract translation: 目的：提供用于蚀刻氧化硅层的组合物，以降低各种氮化物层的蚀刻速率，同时保持呈现衬底的各种氧化硅层的高蚀刻速率。 构成：用于蚀刻氧化硅层的组合物包括氟化氢，阴离子聚合物和去离子水。 阴离子聚合物的含量相对于用于蚀刻氧化硅层的组合物的总量为0.001-2重量％。 氧化硅层对氮化物层的蚀刻选择性为80以上。 阴离子聚合物选自聚丙烯酸，聚磺酸，聚丙烯酰胺/丙烯酸共聚物，聚丙烯酸/磺酸共聚物，聚磺酸/丙烯酰胺共聚物，聚丙烯酸/丙二酸共聚物及其组合。
-
Patent Agency Ranking
公开(公告)号：KR100837325B1
公开(公告)日：2008-06-11
申请号：KR1020070001514
申请日：2007-01-05
Applicant: 삼성전자주식회사 , 부경대학교 산학협력단
IPC: H01L21/302
Abstract: 초임계 유체를 이용한 식각, 세정 및 건조 방법들 및 이를 위한 챔버 시스템을 제공한다. 이 방법은 식각 약품이 용해된 초임계 이산화탄소를 사용하여 물질막을 식각하는 단계 및 세정 약품이 용해된 초임계 이산화탄소를 사용하여 식각 부산물을 제거하는 단계를 포함한다.
-
公开(公告)号：KR1020080043748A
公开(公告)日：2008-05-19
申请号：KR1020080031852
申请日：2008-04-04
Applicant: 삼성전자주식회사 , 부경대학교 산학협력단
IPC: H01L21/302
Abstract: A drying method using a supercritical fluid is provided to enhance productivity by using high reactivity of the supercritical fluid. A material layer is formed(S30). The material layer is processed by using water-soluble chemicals(S32). A wet-rinse process is performed(S33). The water-soluble chemicals are removed by using a supercritical fluid including a supercritical CO2 and a surface active agent(S34). A flushing process is performed by using the supercritical CO2(S35). The material layer is a silicon oxide layer. The process using the water-soluble chemicals includes a process for dipping the material layer into a chemical material including deionized water and fluorine melted in the deionized water.
Abstract translation: 提供使用超临界流体的干燥方法，以通过使用超临界流体的高反应性来提高生产率。 形成材料层（S30）。 通过使用水溶性化学品处理材料层（S32）。 进行湿式漂洗处理（S33）。 通过使用包括超临界CO 2和表面活性剂的超临界流体（S34）除去水溶性化学物质。 通过使用超临界CO 2进行冲洗处理（S35）。 材料层是氧化硅层。 使用水溶性化学品的方法包括将材料层浸入包括在去离子水中熔融的去离子水和氟的化学材料的方法。
-
公开(公告)号：KR1020080012635A
公开(公告)日：2008-02-12
申请号：KR1020060073777
申请日：2006-08-04
Applicant: 삼성전자주식회사
IPC: H01L21/304
Abstract: A substrate drying method is provided to restrain generation of a water mark by sufficiently removing water remaining on a substrate. A substrate cleaned by using a cleaning solution containing deionized water is firstly rinsed by using a dry agent containing a first organic fluorine-based compound and alcohol(S10). The firstly rinsed substrate is secondly rinsed by using an organic fluorine-based compound solvent containing a second organic fluorine-based compound(S20). The organic fluorine-based compound solvent is a solvent from which water is removed. The alcohol is isopropyl alcohol, ethanol or methanol.
Abstract translation: 提供了一种基板干燥方法，通过充分去除残留在基板上的水分来抑制水痕的产生。 首先使用含有第一有机氟系化合物和醇的干燥剂对通过使用含有去离子水的清洗液进行清洗的基板进行清洗（S10）。 首先使用含有第二有机氟系化合物的有机氟系化合物溶剂对第一次冲洗的基材进行第二次冲洗（S20）。 有机氟系化合物溶剂是除去水的溶剂。 醇是异丙醇，乙醇或甲醇。
-
公开(公告)号：KR100757329B1
公开(公告)日：2007-09-11
申请号：KR1020060079998
申请日：2006-08-23
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: H01L21/67057 , H01L21/67034
Abstract: A substrate processing apparatus of a single wafer type is provided to decrease recontamination of a semiconductor substrate while the substrate is processed by using a process solution. A chamber(102) has an opened upper portion and an opened lower portion. A bottom panel(104) is detachably engaged to the opened lower portion. A solution supply unit(110) is connected to the bottom panel to supply a process solution for processing a substrate(10) into the chamber. A substrate holder(122) holds both sides of the substrate to position vertically the substrate in the chamber. The bottom panel is coupled to the lower portion of the chamber by plural coupling members(106).
Abstract translation: 提供单晶片型的基板处理装置，以通过使用处理溶液来处理基板，减少半导体基板的再污染。 室（102）具有敞开的上部和敞开的下部。 底板（104）可拆卸地接合到打开的下部。 解决方案供应单元（110）连接到底板以提供用于将基板（10）加工到室中的处理溶液。 衬底保持器（122）保持衬底的两侧以将衬底垂直定位在腔室中。 底板通过多个联接构件（106）联接到腔室的下部。
-
公开(公告)号：KR1020070067539A
公开(公告)日：2007-06-28
申请号：KR1020050128893
申请日：2005-12-23
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: A flash memory device having a dual floating gate is provided to improve a leakage current characteristic between floating gates and active regions by floating gates composed of lower floating gates having a smaller width than that of the active regions and upper floating gates having a greater width than that of the active regions. An isolation layer is disposed in a substrate to confine a plurality of parallel active regions(115a). Lower floating gates(140a) are two-dimensionally arranged on the active regions, self-aligned with the active regions. Each lower floating gate has a bottom surface having a smaller width than that of the active region. Upper floating gates(145a) cover the lower floating gates to be self-aligned with the lower floating gates wherein each upper floating gate has a greater width than that of the active region. A control gate electrode(160) overlaps the upper surfaces of the upper floating gates, crossing the upper part of the active regions. The upper floating gates can cover a part of the sidewalls of the lower floating gates while covering the upper surfaces of the lower floating gates.
Abstract translation: 提供一种具有双浮置栅极的闪速存储器件，以通过由具有比有源区域的宽度小的下浮动栅极构成的浮动栅极和宽浮动栅极具有较大宽度的浮动栅极来提高浮置栅极和有源区域之间的漏电流特性 活跃区域的。 隔离层设置在衬底中以限制多个平行的有源区（115a）。 下浮动栅极（140a）二维排列在有源区域上，与有源区域自对准。 每个下浮动栅极具有比有源区域的宽度小的底表面。 上浮动栅极（145a）覆盖下浮动栅极以与下浮置栅极自对准，其中每个上浮置栅极具有比有源区域宽的宽度。 控制栅电极（160）与上浮动栅极的上表面重叠，与有源区的上部交叉。 上部浮动栅极可以覆盖下部浮动栅极的侧壁的一部分，同时覆盖下部浮动栅极的上表面。
-
-
-
-
-
-
-
-
-
Search Results
87
records
(took 0.035 seconds)
