公开(公告)号：DE102006015132A1

公开(公告)日：2007-10-11

申请号：DE102006015132

申请日：2006-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHWETLICK WERNER ,  HARTNER WALTER ,  GOTTINGER REINHARD ,  BONART DIETRICH

IPC: H01L29/40 ,  H01L21/74

Abstract: The structure has an electrically insulated deep trench isolation (4) with a semiconductor substrate, and a single-crystal semiconductor layer that is arranged at the semiconductor substrate and a heavily doped buried layer (3). A set of low impedance contacts varies from a surface of the semiconductor layer till the buried layer is in the form of diffusion areas such as decreaser-contact. The deep trench isolation has a meander-shaped course formed in control of bays (8), such that one of the diffusion areas is arranged in one of the bays. An independent claim is also included for a method for manufacturing a semiconductor structure.

公开(公告)号：DE102004057238B4

公开(公告)日：2007-10-04

申请号：DE102004057238

申请日：2004-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOELLNER REINHARD ,  HARTNER WALTER ,  BUSCH JOERG

IPC: H01L23/28 ,  H01L23/52

公开(公告)号：DE102005030638A1

公开(公告)日：2007-01-11

申请号：DE102005030638

申请日：2005-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BONART DIETRICH ,  HARTNER WALTER ,  GRUBER HERMANN ,  MEISER ANDREAS

IPC: H01L27/08 ,  H01L21/28 ,  H01L21/762

公开(公告)号：DE102005020806A1

公开(公告)日：2006-11-23

申请号：DE102005020806

申请日：2005-05-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  BUSCH JOERG ,  GOELLNER REINHARD

IPC: H01L23/28 ,  H01L23/485 ,  H01L23/522

Abstract: The chip has an intermediate oxide layer (1) formed between an upper conductor consisting of aluminum and a lower conductor, and a silicon oxide layer (3) provided on the intermediate oxide layer (1) and the upper conductor (2). A passivation layer (5) made of silicon carbide having high breaking point/tensile strength is provided on the silicon oxide layer, where the thickness of the passivation layer is 100-1,000 nanometer.

公开(公告)号：DE10131490B4

公开(公告)日：2006-06-29

申请号：DE10131490

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/8239 ,  H01L21/02 ,  H01L21/8242

公开(公告)号：DE10131625B4

公开(公告)日：2006-06-14

申请号：DE10131625

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/8239 ,  H01L27/105 ,  H01L21/02 ,  H01L27/115 ,  H01L27/11502

Abstract: To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.

公开(公告)号：DE102004057238A1

公开(公告)日：2006-06-08

申请号：DE102004057238

申请日：2004-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOELLNER REINHARD ,  HARTNER WALTER ,  BUSCH JOERG

IPC: H01L23/28 ,  H01L23/52

Abstract: Semiconductor component comprises a passivation layer (6) over a semiconductor body (1) with a crack-forming structure (10,11) between them that encourages formation of cracks at defined positions (14) within the passivation layer when mechanical stresses arise within the layer.

公开(公告)号：DE69826015D1

公开(公告)日：2004-10-07

申请号：DE69826015

申请日：1998-07-17

Applicant: SYMETRIX CORP ,  INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUNTHER ,  HARTNER WALTER ,  MAZURE CARLOS ,  SOLAYAPPAN NARAYAN ,  JOSHI VIKRAM ,  DERBENWICK F

IPC: C23C18/12 ,  H01L21/314 ,  H01L21/316

Abstract: A liquid precursor containing a metal is applied to a first electrode, dried in air at a first temperature of 160 DEG C. and then a second temperature of 260 DEG C., RTP baked at a temperature of 300 DEG C. in oxygen, RTP baked at a temperature of 650 DEG C. in nitrogen, and annealed at a temperature of 800 DEG C. in nitrogen to form a strontium bismuth tantalate layered superlattice material. A second electrode is deposited and then the device is patterned to form a capacitor, and a second anneal is performed at a temperature of 800 DEG C. in nitrogen. Alternatively, the second anneal may be performed in oxygen at a temperature of 600 DEG C. or less. In this manner, a high electronic quality thin film of a layered superlattice material is fabricated without a high-temperature oxygen anneal.

公开(公告)号：DE10009762B4

公开(公告)日：2004-06-03

申请号：DE10009762

申请日：2000-03-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  BACHHOFER HARALD ,  HOENLEIN WOLFGANG ,  SCHINDLER GUENTHER ,  HARTNER WALTER

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L21/8239

Abstract: Production of a storage capacitor comprises preparing a first electrode layer (1); applying a 1 nm thick CeO2 layer (2) on the electrode layer; applying an amorphous dielectric layer (3) made from SrBi2Ta2O9 (SBT) or SrBi2(TaNb)2O9 (SBTN) on the CeO2 layer; heating at 590-620[deg] C to crystallize the dielectric layer; and applying a second electrode layer (4) on the dielectric layer. An independent claim is also included for a process for the production of a semiconductor component comprising forming a switching transistor on a semiconductor substrate; and forming the storage capacitor on the transistor. Preferred Features: The electrode layers are made from platinum, a conducting oxide of a platinum or an inert and conducting oxide. The dielectric layer is 20-200 nm thick.

公开(公告)号：DE10131625A1

公开(公告)日：2003-01-23

申请号：DE10131625

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L27/105 ,  H01L21/02 ,  H01L27/115 ,  H01L27/11502 ,  H01L21/8239

Abstract: A method for manufacturing a semiconductor storage device, in which a semiconductor substrate or similar, a passivation zone (21) and/or a surface zone (20a, 21a) are formed on it with a CMOS structure and in which in the region of the semiconductor substrate (20) a passivation zone (21) and/or a surface zone (20a, 21a) on it are formed a capacitor arrangement (2) of capacitor devices (10-1...10-4) serving as storage elements. At least one part of the capacitor devices (10-1...10-4) are formed with a number of mutually-parallel connected discrete capacitors (C1,C2).