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    SYSTEMS AND METHODS FOR BLOCKING MICROWAVE PROPAGATION IN PARALLEL PLATE STRUCTURES UTILIZING CLUSTER VIAS
    72.
    发明申请
    SYSTEMS AND METHODS FOR BLOCKING MICROWAVE PROPAGATION IN PARALLEL PLATE STRUCTURES UTILIZING CLUSTER VIAS 审中-公开
    用于阻止采用CLASTER VIAS的平行板结构中的微波传播的系统和方法

    公开(公告)号：WO2005104149A1

    公开(公告)日：2005-11-03

    申请号：PCT/US2005/013235

    申请日：2005-04-19

    Applicant: WEMTEC, INC. ,  MCKINZIE, William, E., III

    Inventor： MCKINZIE, William, E., III

    IPC: H01G4/35

    CPC classification number: H01G4/35 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/16 ,  H01P1/2005 ,  H01P1/211 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/0239 ,  H05K1/115 ,  H05K1/116 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/09809 ,  H01L2924/00

    Abstract: Systems and methods are taught for blocking the propagation of electromagnetic waves in parallel-plate waveguide (PPW) structures. Periodic arrays of resonant vias are used to create broadband high frequency stop bands in the PPW, while permitting DC and low frequency waves to propagate. Particular embodiments include clusters of small vias that effectively function as one large via, thereby increasing stop band bandwidth and maximizing parallel plate capacitance. Cluster vias can be configured to additionally provide a shielded and impedance matched route within the interior area of the cluster through which signal vias can connect transmission lines disposed in planes lying above and below the PPW. Important applications include electromagnetic noise reduction in layered electronic devices such as circuit boards, ceramic modules, and semiconductor chips.

    Abstract translation: 教导系统和方法阻止平行板波导（PPW）结构中电磁波的传播。 谐振通孔的周期性阵列用于在PPW中产生宽带高频阻带，同时允许DC和低频波传播。 具体实施例包括有效地用作一个大通孔的小通孔簇，从而增加阻带带宽并最大化平行板电容。 集群通孔可以被配置为在簇的内部区域内另外提供屏蔽和阻抗匹配的路由，信号通孔可以通过该通孔连接布置在PPW上方和下方的平面中的传输线。 重要的应用包括诸如电路板，陶瓷模块和半导体芯片的分层电子设备中的电磁降噪。

    TELESCOPING BLIND VIA IN THREE-LAYER CORE
    73.
    发明申请
    TELESCOPING BLIND VIA IN THREE-LAYER CORE 审中-公开
    通过三层核心引导盲人

    公开(公告)号：WO2005036940A1

    公开(公告)日：2005-04-21

    申请号：PCT/US2004/033012

    申请日：2004-10-08

    Applicant: QUALCOMM INCORPORATED ,  MATTIX, Dwight, W.

    Inventor： MATTIX, Dwight, W.

    IPC: H05K1/11

    CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4602 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/096 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/51 ,  Y10T29/52 ,  Y10T29/5317

    Abstract: A multilayer PCB including at least one carrier, wherein the at least one carrier comprises a pseudo three-layer core (110). Each three-layer core (110) includes a first metal layer (120), a first dielectric layer (124), an internal bridge layer (126), a second dielectric layer (125), and a second metal layer (122). The bridge layer includes a plurality of bridge pads (134). Each carrier includes a plurality of interlayer interconnection units (150a, 150n) for interconnecting the first and second metal layers. Each interlayer interconnection unit comprises a pair of opposed blind vias (140, 142) and a bridge pad (134) disposed between, and in electrical contact with, the pair of blind vias.

    Abstract translation: 包括至少一个载体的多层PCB，其中所述至少一个载体包括伪三层芯（110）。 每个三层芯（110）包括第一金属层（120），第一介电层（124），内部桥接层（126），第二介电层（125）和第二金属层（122）。 桥接层包括多个桥接焊盘（134）。 每个载体包括用于互连第一和第二金属层的多个层间互连单元（150a，150n）。 每个层间互连单元包括一对相对的盲孔（140,142）和布置在一对盲孔之间并与之接触的桥接垫（134）。

    PASSIVE TRANSMISSION LINE EQUALIZATION USING CIRCUIT-BOARD THRU-HOLES
    74.
    发明申请
    PASSIVE TRANSMISSION LINE EQUALIZATION USING CIRCUIT-BOARD THRU-HOLES 审中-公开
    使用电路板THRH-HOLES的被动传输线均衡

    公开(公告)号：WO03073808A8

    公开(公告)日：2005-04-07

    申请号：PCT/US0227987

    申请日：2002-09-03

    Applicant: FORCE10 NETWORKS INC

    Inventor： GOERGEN JOEL R

    IPC: H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  H05K3/42 ,  H05K3/46 ,  H05K7/14

    CPC classification number: H05K1/0245 ,  H05K1/0248 ,  H05K1/116 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4641 ,  H05K7/1459 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09718

    Abstract: A high-speed router backplane, and method for its fabrication, are disclosed. The backplane uses differential signaling trace pairs on multiple high-speed signaling layers, the high-speed signaling layers separated by ground planes. Plated signaling thru-holes connect the trace pairs to the board surface for connection to external components. The signaling thru-holes pass through clearances in each ground plane. At selected ground planes, a conductive pad is patterned within each high-speed signaling thru-hole clearance, the pad slightly larger than the thru-hole diameter. The pads affect the impedance characteristics of the thru-holes, thus providing a better impedance match to the differential trace pairs, reducing signal reflections, and improving the ability to signal across the backplane at high speeds.

    Abstract translation: 公开了一种高速路由器背板及其制造方法。 背板在多个高速信号层上使用差分信令跟踪对，高速信号层由接地层分开。 电镀信号通孔将走线对连接到电路板表面，以连接到外部组件。 信号通孔穿过每个接地平面内的间隙。 在选定的接地平面，每个高速信号通孔间隙内的导电焊盘都被图案化，焊盘略大于通孔直径。 这些焊盘影响通孔的阻抗特性，从而为差分走线对提供更好的阻抗匹配，减少信号反射，并提高高速信号跨背板的能力。

    回路基板及び電子機器
    75.
    发明申请
    回路基板及び電子機器 审中-公开
    电路板和电子设备

    公开(公告)号：WO2003063563A1

    公开(公告)日：2003-07-31

    申请号：PCT/JP2003/000259

    申请日：2003-01-15

    Applicant: 日本電気株式会社 ,  石塚 直美 ,  河野 英一

    Inventor： 石塚 直美 ,  河野 英一

    IPC: H05K3/46

    CPC classification number: H05K1/116 ,  H05K3/3447 ,  H05K3/3463 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09781

    Abstract: A circuit board free of wall separation and land separation even if a part is mounted by soldering using leadless solder. A circuit board (10) comprises N (N >= 3) layers electrically insulated from one another and has a through hole (14) into which an electrode (19) of an electronic part (18) is inserted. On the first and N-th layers, surface layer lands (15) are formed. On the inner wall of the through hole (14), a conductive layer (17) electrically connected to the surface layer lands (15)is formed. The electronic part (18) is so mounted as to be connected to the through hole (14) by filling the through hole (14) with leadless solder (20). At least one inner layer land (16) extending from the conductive layer (17) is formed in the same layer as the circuit of the M-th (M is an integer satisfying the relation 2

    Abstract translation: 即使通过使用无铅焊料进行焊接安装了部件，也不需要墙壁分离和接地分离的电路板。 电路板（10）包括彼此电绝缘的N（N> = 3）层，并且具有插入电子部件（18）的电极（19）的通孔（14）。 在第一层和第N层上，形成表层层（15）。 在通孔（14）的内壁上形成与表面层焊盘（15）电连接的导电层（17）。 通过用无铅焊料（20）填充通孔（14），电子部件（18）被安装成连接到通孔（14）。 从导电层（17）延伸的至少一个内层平台（16）形成在与第M个电路相同的层（M是满足关系式2 <= M <=（N-1） ）层。 内层焊盘（16）不与内层焊盘（16）的电路电连接。

    MULTILAYER PRINTED WIRING BOARD
    80.
    发明授权
    MULTILAYER PRINTED WIRING BOARD 有权
    多层印刷线路板

    公开(公告)号：EP1845762B1

    公开(公告)日：2011-05-25

    申请号：EP06712598.9

    申请日：2006-01-30

    Applicant: IBIDEN CO., LTD.

    Inventor： WU, Youhong

    IPC: H05K3/46 ,  H05K3/18

    CPC classification number: H05K1/115 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: [PROBLEMS] To provide a multilayer printed wiring board which does not deteriorate connection reliability by forming a filled via directly above a small-diameter filled via. [MEANS FOR SOLVING PROBLEMS] A stress applied on the filled via (60) formed on covering plating layers (36a, 36d) is larger than that applied on a filled via (160) formed on a second interlayer resin insulating layer (150) during a heat cycle. Thus, a bottom diameter (d1) of the filled via (60) is made larger than a bottom diameter (d2) of the filled via (160) formed directly above.

    Abstract translation: 本发明提供一种多层印刷线路板，其通过在小直径填充通路正上方形成填充通路而不会使连接可靠性降低。 [解决问题的方法]施加在形成在覆盖镀层（36a，36d）上的填充通孔（60）上的应力大于施加在形成在第二层间树脂绝缘层（150）上的填充通孔（160） 一个热循环。 因此，填充通孔（60）的底部直径（d1）大于直接形成在上方的填充通孔（160）的底部直径（d2）。

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