公开(公告)号：US06243253B1

公开(公告)日：2001-06-05

申请号：US09264124

申请日：1999-03-08

Applicant: David A. DuPre ,  John L. Galvagni ,  Andrew P. Ritter

Inventor： David A. DuPre ,  John L. Galvagni ,  Andrew P. Ritter

IPC: H01G4228

CPC classification number: H01G2/065 ,  H01G4/30 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/10045 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: A multilayer ceramic device suitable for use in surface mount decoupling applications may have a single capacitor or a capacitor array. The device has a capacitor body defining a plurality of electrical terminals on an outer surface thereof. The terminals are interdigitated such that a respective first polarity terminal will be adjacent to a respective second polarity terminal (and vice versa). The capacitor body contains a plurality of interleaved capacitor plates in opposed and spaced apart relation. Capacitor plates of the first polarity are electrically connected to respective first polarity terminals via a plurality of lead structures. Likewise, a plurality of lead structures electrically connect capacitor plates of the second polarity to respective second polarity terminals.

Abstract translation: 适用于表面贴装去耦应用的多层陶瓷器件可以具有单个电容器或电容器阵列。 该装置具有在其外表面上限定多个电端子的电容器主体。 端子相互交错，使得相应的第一极性端子将与相应的第二极性端子相邻（反之亦然）。 电容器主体包含相互间隔开的多个交错电容器板。 第一极性的电容器板经由多个引线结构电连接到相应的第一极性端子。 同样地，多个引线结构将第二极性的电容器板电连接到相应的第二极性端子。

公开(公告)号：US06201502B1

公开(公告)日：2001-03-13

申请号：US09378522

申请日：1999-08-20

Applicant: Junichi Kurita ,  Atsuyuki Yuasa ,  Kazunari Kawahata

Inventor： Junichi Kurita ,  Atsuyuki Yuasa ,  Kazunari Kawahata

IPC: H01Q124

CPC classification number: H01Q9/0421 ,  H01Q1/243 ,  H01Q1/38 ,  H05K1/0243 ,  H05K1/115 ,  H05K2201/0715 ,  H05K2201/09481 ,  H05K2201/0979 ,  H05K2201/10636 ,  H05K2201/10969 ,  Y02P70/611

Abstract: An antenna includes: a base having opposing first and second surfaces and opposing end surfaces; a radiation electrode covering at least a portion of the first major surface of the base; a power terminal disposed on the base and operable to conduct signal power which is at least one of received and transmitted by the antenna; a mounting substrate having spaced apart first and second major surfaces; a first ground electrode covering at least a portion of the second major surface of the base, wherein the base is disposed on the mounting substrate such that the second major surface of the base is coupled to the first major surface of the mounting substrate and a distance D is defined from the first major surface of the base to the second major surface of the mounting substrate, and the first ground electrode is electrically coupled to the first ground electrode such that a gain of the antenna is a function of the distance

Abstract translation: 天线包括：具有相对的第一和第二表面和相对端表面的基座; 辐射电极，其覆盖所述基底的所述第一主表面的至少一部分; 电源终端，其设置在所述基座上并且可操作以传导至少由天线接收和传输的信号功率; 安装基板，具有间隔开的第一和第二主表面; 覆盖所述基座的所述第二主表面的至少一部分的第一接地电极，其中所述基座设置在所述安装基板上，使得所述基座的所述第二主表面耦合到所述安装基板的所述第一主表面， D从基座的第一主表面到安装基板的第二主表面限定，并且第一接地电极电耦合到第一接地电极，使得天线的增益是距离的函数

公开(公告)号：US6060339A

公开(公告)日：2000-05-09

申请号：US902470

申请日：1997-07-29

Applicant: Salman Akram ,  James M. Wark ,  David R. Hembree

Inventor： Salman Akram ,  James M. Wark ,  David R. Hembree

IPC: H01L23/538 ,  H05K1/00 ,  H05K3/22 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/5382 ,  H01L24/97 ,  H05K1/0292 ,  H05K1/0295 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/14 ,  H05K2201/0979 ,  H05K2201/10159 ,  H05K2201/10674

Abstract: A method and apparatus for repair of a multi-chip module such as a memory module is provided, where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.

Abstract translation: 提供了一种用于修复诸如存储器模块的多芯片模块的方法和装置，其中至少一个冗余或辅助芯片连接位置设置在多芯片模块的基板上。 辅助芯片安装位置优选地提供用于连接多于一种类型的替换半导体芯片的触点。 因此，当发现多芯片模块上的一个或多个芯片完全或部分缺陷时，可以选择至少一个替换芯片并附加到辅助位置，以提供额外的存储器以使模块回到其设计能力。

公开(公告)号：US5975944A

公开(公告)日：1999-11-02

申请号：US878561

申请日：1997-06-19

Applicant: Thomas John Medina ,  Paul Christian Sprunger

Inventor： Thomas John Medina ,  Paul Christian Sprunger

IPC: H01R9/05 ,  H01R31/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/28 ,  H05K3/34 ,  H01R9/07

CPC classification number: H01R31/06 ,  H01R9/0515 ,  H05K1/117 ,  H05K3/3405 ,  H01R23/6873 ,  H01R31/005 ,  H05K1/0268 ,  H05K1/0293 ,  H05K1/118 ,  H05K2201/09354 ,  H05K2201/0979 ,  H05K2201/10356 ,  H05K2203/175 ,  H05K3/0052 ,  H05K3/281 ,  Y10S439/912

Abstract: An electrical connector (1) constructed with a carrier (2) on which circuit traces (8) attach to signal transmitting conductors (4) of electrical cables (3), an opening (12) through the carrier (2) at which conductors (4) of the cables (3) project for electrical connection to an electrical circuit positioned at the opening (12), and the traces (8) having different portions (15,21,24) that are spaced apart on different pitch spacing for connection to respective signal transmitting conductors that are spaced apart on corresponding different pitch spacings. The traces (8) may include test pads (13) in registration with windows (19) in the carrier (2).

Abstract translation: 一种由载体（2）构成的电连接器（1），电路迹线（8）附接到电缆（3）的信号传输导体（4），穿过载体（2）的开口（12） 电缆（3）的突出部分（4）突出，用于电连接到位于开口（12）处的电路，并且具有不同部分（15,21,24）的迹线（8）以不同的间距分隔开，用于连接 对应于相应的不同间距间隔隔开的相应的信号传输导体。 迹线（8）可以包括与载体（2）中的窗口（19）对准的测试焊盘（13）。

公开(公告)号：US5973929A

公开(公告)日：1999-10-26

申请号：US974510

申请日：1997-11-19

Applicant: Tomoyasu Arakawa ,  Toru Otaki ,  Yasushi Takeuchi ,  Hideho Inagawa ,  Yoshimi Terayama ,  Tohru Ohsaka

Inventor： Tomoyasu Arakawa ,  Toru Otaki ,  Yasushi Takeuchi ,  Hideho Inagawa ,  Yoshimi Terayama ,  Tohru Ohsaka

IPC: H01G4/12 ,  H01G4/228 ,  H01G4/255 ,  H01G4/40 ,  H05K1/11 ,  H05K1/16 ,  H05K3/42 ,  H01G4/35

CPC classification number: H05K1/115 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/0979 ,  H05K2201/09809 ,  H05K3/429 ,  H05K3/4688

Abstract: A circuit board having a printed capacitor whose capacitance is easily adjusted includes a plurality of through-holes arranged in arrays and electrically connected to each other via conductive films. Therefore, first and second electrode portions are arranged to oppose each other, and form a printed capacitor. The capacitance of the capacitor can be adjusted by the number and diameter of through-holes, and the interval between each two adjacent through-holes. Therefore, even when a large-capacitance capacitor is to be formed, the printed capacitor can be rendered compact.

Abstract translation: 电容容易调节的具有印刷电容器的电路板包括排列成阵列并通过导电膜彼此电连接的多个通孔。 因此，第一电极部分和第二电极部分彼此相对布置，并形成印刷电容器。 电容器的电容可以通过通孔的数量和直径以及两个相邻通孔之间的间隔进行调整。 因此，即使要形成大容量电容器，印刷电容器也可以变得紧凑。

公开(公告)号：US5797757A

公开(公告)日：1998-08-25

申请号：US747701

申请日：1996-11-12

Applicant: Yoshihito Aoki

Inventor： Yoshihito Aoki

IPC: H01R24/00 ,  H01R13/621 ,  H01R31/08 ,  H05K1/02 ,  H05K1/14 ,  H05K3/10 ,  H05K3/20 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H01R4/66 ,  H01R13/648

CPC classification number: H01R12/7088 ,  H01R12/716 ,  H01R12/724 ,  H01R12/73 ,  H05K1/0263 ,  H05K1/141 ,  H01R13/6215 ,  H01R31/085 ,  H05K2201/0979 ,  H05K2201/10189 ,  H05K2201/10272 ,  H05K2201/10303 ,  H05K2201/10924 ,  H05K3/107 ,  H05K3/202 ,  H05K3/325 ,  H05K3/3447 ,  H05K3/368

Abstract: A PCB multi-pole connector including a connector body, a plurality of terminals mounted in the connector body, the terminals having first end portions for mating with terminals of a mating connector and second end portions for connecting with circuit patterns formed on printed circuit boards, and a bus bar card accommodating a bus bar, the bus bar card including upper and lower cases having cut portions, the bus bar including a terminal portion and a connecting portion having a cut portion, in which the bus bar card is detachably mounted in the connector body to juxtapose the terminal portion with the first end portions of the terminals, the connecting portion of the bus bar is electrically connected to at least one of the circuit patterns of the printed circuit boards with an auxiliary member.

Abstract translation: 一种PCB多极连接器，包括连接器主体，安装在连接器主体中的多个端子，所述端子具有用于与配合连接器的端子配合的第一端部和用于连接印刷电路板上形成的电路图案的第二端部， 汇流条卡包括汇流条，汇流条卡包括具有切割部分的上壳体和下壳体，母线包括端子部分和具有切口部分的连接部分，其中母线卡可拆卸地安装在所述母线 连接器本体将端子部分与端子的第一端部并置，母线的连接部分与辅助部件电连接到印刷电路板的至少一个电路图案。

公开(公告)号：US5605223A

公开(公告)日：1997-02-25

申请号：US500961

申请日：1995-08-02

Applicant: Klaus Gutmann ,  Hans-Werner Luckehe

Inventor： Klaus Gutmann ,  Hans-Werner Luckehe

IPC: H01H13/70 ,  H01H13/785 ,  H05K1/11 ,  H05K3/24 ,  H01H1/06

CPC classification number: H01H13/785 ,  H01H13/7006 ,  H05K1/11 ,  H01H2201/026 ,  H01H2201/03 ,  H01H2203/038 ,  H01H2203/054 ,  H05K2201/0323 ,  H05K2201/09418 ,  H05K2201/0979 ,  H05K2201/10053 ,  H05K3/245

Abstract: In order to produce keyboards, two pairs of diagonally connected squares with rounded corners are used as fixed contacts. A direct diagonal connection electrically connects two non-adjacent squares. The squares are conductive lacquer (carbon lacquer) and cover copper pads on a printed circuit board.

Abstract translation: PCT No.PCT / DE93 / 01197 Sec。 371日期：1995年8月2日 102（e）日期1995年8月2日PCT 1993年11月15日PCT公布。 第WO94 / 17541号公报 日期1994年8月4日为了生产键盘，使用两对带有圆角的对角线连接的正方形作为固定触点。 直接对角连接电连接两个不相邻的正方形。 正方形是导电漆（碳漆），并覆盖印刷电路板上的铜焊盘。

公开(公告)号：US5420378A

公开(公告)日：1995-05-30

申请号：US274872

申请日：1994-07-14

Applicant: H. Scott Estes ,  Michael Ohlinger ,  N. Deepak Swamy

Inventor： H. Scott Estes ,  Michael Ohlinger ,  N. Deepak Swamy

IPC: H05K1/11 ,  H05K3/32 ,  H05K3/34 ,  H05K3/42 ,  H05K9/00 ,  H05K1/18 ,  H05K7/04

CPC classification number: H05K9/0039 ,  H05K1/0215 ,  H05K1/115 ,  H05K3/3452 ,  H05K2201/09572 ,  H05K2201/0979 ,  H05K2201/099 ,  H05K2201/10393 ,  H05K2201/10409 ,  H05K3/325 ,  H05K3/429

Abstract: To facilitate a grounding connection between a circuit board and a chassis upon which it is to be mounted, a spaced series of unlined mounting holes are formed through the substrate portion of the circuit board between its top and bottom sides, and spaced series of grounding vias are formed through the substrate and positioned in a circular arrays around each of the mounting holes. Annular layers of a metallic plating material are formed on the opposite sides of the circuit board substrate, around the top and bottom ends of the unlined mounting holes, with the plating material being extended along the interior side surfaces of the vias between associated top and bottom annular plating material layers. Using solder masks placed on the opposite sides of the circuit board substrate, circular arrays of solder pads are formed on the outer side surfaces of the annular plating layers, with each solder pad array being interdigitated with the vias in one of the circular arrays thereof, and being horizontally offset from the vias. The bottom side of the circuit board is secured against a side of the chassis by extending metal mounting screws through the unlined mounting holes of the circuit board and threading the screws into corresponding holes in the chassis to press the bottom side solder pads of the circuit board against the chassis.

Abstract translation: 为了便于电路板与要安装在其上的底盘之间的接地连接，在其顶侧和底侧之间通过电路板的基板部分形成间隔的一系列无内衬的安装孔，并且间隔开的一系列接地通孔 通过基板形成并围绕每个安装孔定位成圆形阵列。 在电路板基板的相对侧上，围绕无衬里的安装孔的顶端和底端形成金属电镀材料的环形层，电镀材料沿相连的顶部和底部之间的通孔的内侧表面延伸 环形电镀层。 使用放置在电路板基板的相对侧上的焊接掩模，在环形镀层的外侧表面上形成圆形阵列的焊盘，每个焊盘阵列与其中一个圆形阵列中的通孔相互交错， 并且与通孔水平地偏移。 通过将金属安装螺钉穿过电路板的无衬里安装孔，将电路板的底部固定在机箱的一侧，并将螺丝拧入机箱中相应的孔，以将电路板的底面焊盘 对着底盘。

公开(公告)号：US5408053A

公开(公告)日：1995-04-18

申请号：US160015

申请日：1993-11-30

Applicant: Brian D. Young

Inventor： Brian D. Young

IPC: H01P3/08 ,  H05K1/02 ,  H05K1/03 ,  H05K3/40 ,  H05K3/46 ,  H05K1/00

CPC classification number: H01P3/088 ,  H05K1/0219 ,  H05K1/0265 ,  H05K1/0306 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K3/4053 ,  H05K3/4611 ,  H05K3/4629

Abstract: A transmission line structure including a central signal conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers of a unitized multilayer circuit structure, a first ground conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers and laterally separated from one side of the central signal conductor stack, and a second ground conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers and laterally separated from another side of the central signal conductor stack such that the central conductor stack is laterally between the first and second ground conductor stacks.

Abstract translation: 传输线结构，其包括由单位化多层电路结构的连续电介质层彼此分离的细长导电条的中心信号导体叠层，细长导电条的第一接地导体堆叠，其由连续的电介质层彼此分离并且横向分离 中心信号导体叠层的一侧和细长导电条的第二接地导体叠层，它们由连续的电介质层彼此分开，并与中心信号导体堆叠的另一侧横向分离，使得中心导体堆叠横向位于第一 和第二接地导体堆叠。

公开(公告)号：US5339269A

公开(公告)日：1994-08-16

申请号：US922266

申请日：1992-07-30

Applicant: Yuichi Takagi

Inventor： Yuichi Takagi

IPC: H01L27/10 ,  G11C5/14 ,  G11C11/401 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/0216 ,  G11C5/14 ,  H05K1/112 ,  H05K1/117 ,  H05K2201/093 ,  H05K2201/0979 ,  H05K2201/10159 ,  H05K3/429

Abstract: A memory module includes electrodes arranged on one side edge of a laminated substrate. A plurality of memory elements are mounted on the surface of the laminated substrate, wherein signal line electrodes for the memory elements are arranged on one side edge of the laminated substrate, and respective electrode terminals for a second power supply line and a second grounding line connected in parallel to a first power supply line and a first grounding line are provided on a surface of the laminated substrate. The electrodes are situated at a position at or near maximum amplitude of the potential distribution generated on the first power supply line and the first grounding line when the memory elements are driven.

Abstract translation: 存储模块包括布置在层压基板的一个侧边上的电极。 多个存储元件安装在层压基板的表面上，其中用于存储元件的信号线电极布置在层叠基板的一个侧边上，并且用于第二电源线和第二接地线的各个电极端子连接 并联于第一电源线和第一接地线设置在层叠基板的表面上。 当存储元件被驱动时，电极位于在第一电源线和第一接地线上产生的电位分布的最大幅度处或最接近的位置处。